JAJSLN3B
March 2021 – October 2021
TPS61379-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagrams
8.3
Feature Description
8.3.1
VCC Power Supply
8.3.2
Input Undervoltage Lockout (UVLO)
8.3.3
Enable and Soft Start
8.3.4
Shut Down
8.3.5
Switching Frequency Setting
8.3.6
Spread Spectrum Frequency Modulation
8.3.7
Bootstrap
8.3.8
Load Disconnect
8.3.9
MODE/SYNC Configuration
8.3.10
Overvoltage Protection (OVP)
8.3.11
Output Short Protection/Hiccup
8.3.12
Power-Good Indicator
8.3.13
Thermal Shutdown
8.4
Device Functional Modes
8.4.1
Forced PWM Mode
8.4.2
Auto PFM Mode
8.4.3
External Clock Synchronization
8.4.4
Down Mode
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Programming the Output Voltage
9.2.2.2
Setting the Switching Frequency
9.2.2.3
Selecting the Inductor
9.2.2.4
Selecting the Output Capacitors
9.2.2.5
Selecting the Input Capacitors
9.2.2.6
Loop Stability and Compensation
9.2.2.6.1
Small Signal Model
9.2.2.6.2
Loop Compensation Design Steps
9.2.2.6.3
Selecting the Bootstrap Capacitor
9.2.2.6.4
VCC Capacitor
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Third-Party Products Disclaimer
12.2
Receiving Notification of Documentation Updates
12.3
サポート・リソース
12.4
Trademarks
12.5
用語集
12.6
静電気放電に関する注意事項
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RTE|16
MPQF149D
サーマルパッド・メカニカル・データ
RTE|16
QFND630A
発注情報
jajsln3b_oa
jajsln3b_pm
9.2.2.6
Loop Stability and Compensation