JAJSLN3B March   2021  – October 2021 TPS61379-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  VCC Power Supply
      2. 8.3.2  Input Undervoltage Lockout (UVLO)
      3. 8.3.3  Enable and Soft Start
      4. 8.3.4  Shut Down
      5. 8.3.5  Switching Frequency Setting
      6. 8.3.6  Spread Spectrum Frequency Modulation
      7. 8.3.7  Bootstrap
      8. 8.3.8  Load Disconnect
      9. 8.3.9  MODE/SYNC Configuration
      10. 8.3.10 Overvoltage Protection (OVP)
      11. 8.3.11 Output Short Protection/Hiccup
      12. 8.3.12 Power-Good Indicator
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced PWM Mode
      2. 8.4.2 Auto PFM Mode
      3. 8.4.3 External Clock Synchronization
      4. 8.4.4 Down Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Output Voltage
        2. 9.2.2.2 Setting the Switching Frequency
        3. 9.2.2.3 Selecting the Inductor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Input Capacitors
        6. 9.2.2.6 Loop Stability and Compensation
          1. 9.2.2.6.1 Small Signal Model
          2. 9.2.2.6.2 Loop Compensation Design Steps
          3. 9.2.2.6.3 Selecting the Bootstrap Capacitor
          4. 9.2.2.6.4 VCC Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 用語集
    6. 12.6 静電気放電に関する注意事項
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

TJ = -40 to 125°C, L = 1 µH, VIN = 3.3 V and VOUT = 9 V (VO pin). Typical values are at TJ = 25°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VIN Input voltage range 2.3 14 V
VIN_UVLO VIN under voltage lockout threshold VIN  rising 2.2 2.3 V
VIN  falling 2.04 2.2 V
VIN_HYS VIN UVLO hysteresis 160 mV
VCC_UVLO VCC UVLO threshold VCC rising 2.2 V
VCC_HYS VCC UVLO hysteresis VCC hysteresis 150 mV
VCC VCC regulation IVCC = 6 mA, VOUT = 9V 4.8 V
IQ Quiescent current into VIN pin IC enabled, no load,
VIN = 3.3 V, VOUT = 18.5 V, VFB = VREF + 0.1 V		 25 35 µA
IQ Quiescent current into OUT pin IC enabled, no load,
VIN = 3.3 V, VOUT = 18.5 V, VFB = VREF + 0.1 V		 10 20 µA
ISD Shutdown current into VIN pin IC disabled, VIN = 14 V, EN = GND 0.6 5 µA
ISW_LKG Leakage current into SW IC disabled, VIN = OUT = SW = 14 V 5 µA
IVO_LKG Reverse leakage current into VO IC disabled, OUT= VO = 5 V, SW = 0 5 µA
OUTPUT VOLTAGE
VOVP Output over-voltage protection threshold VIN  = 3.3 V, VOUT rising 19.3 20 20.5 V
VOVP_HYS Output over-voltage protection hysteresis VIN = 3.3 V, OVP threshold 0.5 V
VOLTAGE REFERENCE
VREF Reference Voltage at FB pin TJ = -40 to 125°C, RFB = 16.0 kΩ 0.788 0.800 0.812 V
VOUT_5V TJ = -40 to 125°C, RFB = 2.0 kΩ 4.85 5.00 5.15 V
VOUT_5.25V  TJ = -40 to 125°C, RFB = 4.0 kΩ 5.10 5.25 5.35 V
VOUT_5.5V TJ = -40 to 125°C, RFB = 8.0 kΩ 5.35 5.50 5.65 V
IFB_LKG Leakage current into FB pin 50 nA
POWER SWITCH
RDS(on) Low-side MOSFET on resistance VCC = 4.85 V 50 mΩ
RDS(on) High-side MOSFET on resistance VCC = 4.85 V 50 mΩ
RDS(on) Isolation MOSFET on resistance VCC = 4.85 V 100 mΩ
CURRENT LIMIT
ILIM_SW Peak switching current limit Auto PFM Duty cycle = 65% 1.58 2 2.25 A
ILIM_SW Peak switching current limit FPWM Duty cycle = 65% 1.58 2 2.25 A
SWITCHING FREQUENCY
Fsw Switching frequency RFREQ = 18 kΩ 2050 2200 2400 kHz
Fsw Switching frequency RFREQ = 218 kΩ 180 200 230 kHz
Dmax Maximum Duty Cycle RFREQ = 18 kΩ 78 %
tON_min Minimal on time 70 ns
FDITHER 10% Fsw
Fpattern 0.4% Fsw
ERROR AMPLIFIER
ISINK COMP pin sink current VFB = VREF + 0.2V 6 uA
ISOURCE COMP pin source current VFB = VREF - 0.2V 6 uA
VCCLPH COMP pin high clamp voltage VFB = VREF - 0.2 V, ILIM = 2 A 1 V
VCCLPL COMP pin low clamp voltage VFB = VREF + 0.2 V, 0.6 V
GmEA Error amplifier trans conductance VCOMP = 1.0 V 70 uS
POWER GOOD
VPG_TH PG threhold for rising FB voltage Reference to VREF 90%
VPG_HYS PG hysteresis Reference to VREF 5%
IPG_SINK PG pin sink current capability VPG = 0.4 V 20 mA
tPG_DELAY PG delay time 2.5 3.4 4.3 ms
DOWN MODE
tEN_DELAY Delay time between EN high and device working 0.4 ms
tSS Softstart time 2.5 ms
tHCP_ON Hiccup on time 1.8 ms
tHCP_OFF Hiccup off  time 67 ms
SYNC TIMING
fSYNC_MIN 200 kHz
fSYNC_MAX 2200 kHz
EN/SYNC LOGIC
VIH EN, MODE/SYNC pins Logic high threshold 1.2 V
VIL EN, MODE/SYNC pins Logic Low threshold 0.4 V
RDOWN EN, MODE/SYNC pins internal pull down resistor 800 kΩ
THERMAL SHUTDOWN
tSD_R Thermal shutdown rising threshold TJ rising 165 °C
tSD_F Thermal shutdown falling threshold TJ falling 145 °C