SLVS294F September   2000  – August 2015 TPS62000 , TPS62002 , TPS62003 , TPS62004 , TPS62005 , TPS62006 , TPS62007 , TPS62008

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low Noise Antiringing Switch
      2. 8.3.2 Enable
      3. 8.3.3 Undervoltage Lockout
      4. 8.3.4 Power Good Comparator
    4. 8.4 Device Functional Modes
      1. 8.4.1 Soft Start
      2. 8.4.2 Synchronization, Power Save Mode, and Forced PWM Mode
      3. 8.4.3 100% Duty Cycle Operation
      4. 8.4.4 No Load Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Standard 5-V to 3.3-V/600-mA Conversion; High Efficiency
      2. 9.3.2 Single Li-ion to 2.5-V/600-mA Using Ceramic Capacitors Only
      3. 9.3.3 Single Li-ion to 1.8 V/300 mA; Smallest Solution Size
      4. 9.3.4 Dual Cell NiMH or NiCd to 1.2 V/200 mA; Smallest Solution Size
      5. 9.3.5 Dynamic Output Voltage Programming As Used in Low Power DSP Applications
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Related Links
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DGS|10
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

DGS Package
10-Pin VSSOP
Top View
TPS62000 TPS62001 TPS62002 TPS62003 TPS62004 TPS62005 TPS62006 TPS62007 TPS62008 po_dgs_lvs294_01.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
EN 8 I Enable. A logic high enables the converter, logic low forces the device into shutdown mode reducing the supply current to less than 1 μA.
FB 5 I Feedback pin for the fixed output voltage option. For the adjustable version an external resistive divider is connected to FB. The internal voltage divider is disabled for the adjustable version.
FC 2 — Supply bypass pin. A 0.1-μF coupling capacitor should be connected as close as possible to this pin for good high frequency input voltage supply filtering.
GND 3 — Ground
ILIM 6 I Switch current limit. Connect ILIM to GND to set the switch current limit to typically 600 mA, or connect this pin to VIN to set the current limit to typically 1200 mA.
L 9 I/O Connect the inductor to this pin. L is the switch pin connected to the drain of the internal power MOSFETS.
PG 4 O Power good comparator output. This is an open-drain output. A pull-up resistor should be connected between PG and VOUT. The output goes active high when the output voltage is greater than 92% of the nominal value.
PGND 10 — Power ground. Connect all power grounds to PGND.
SYNC 7 I Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an external clock signal with CMOS level:
SYNC = High: Low-noise mode enabled, fixed frequency PWM operation is forced
SYNC = Low (GND): Power save mode enabled, PFM/PWM mode enabled
VIN 1 I Supply voltage input