SLVS833E March   2010  – October 2020 TPS62065 , TPS62067

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Mode Selection (TPS62065)
      2. 8.3.2 Power Good Output (TPS62067)
      3. 8.3.3 Enable
      4. 8.3.4 Clock Dithering
      5. 8.3.5 Undervoltage Lockout
      6. 8.3.6 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Soft Start
      2. 8.4.2 Power Save Mode
      3. 8.4.3 Dynamic Voltage Positioning
      4. 8.4.4 100% Duty Cycle Low Dropout Operation
      5. 8.4.5 Internal Current Limit and Fold-Back Current Limit for Short Circuit Protection
      6. 8.4.6 Output Capacitor Discharge
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Setting
        2. 9.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Output Capacitor Selection
          3. 9.2.2.2.3 Input Capacitor Selection
        3. 9.2.2.3 Checking Loop Stability
      3. 9.2.3 Application Curves
    3. 9.3 System Example
      1. 9.3.1 TPS62067 Adjustable 1.8-V Output
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-CF4265F2-C47F-4157-976D-0E739FA30C28-low.gifFigure 6-1 DSG Package8-Pin WSONTop View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
AGND 3 I Analog GND supply pin for the control circuit.
AVIN 7 I Analog VIN power supply for the control circuit. Must be connected to PVIN and input capacitor.
EN 5 I This is the enable pin of the device. Pulling this pin to low forces the device into shutdown mode. Pulling this pin to high enables the device. This pin must be terminated
FB 4 I Feedback pin for the internal regulation loop. Connect the external resistor divider to this pin. In case of fixed output voltage option, connect this pin directly to the output capacitor
MODE 6 I MODE: MODE pin = High forces the device to operate in fixed frequency PWM mode. MODE pin = Low enables the power save mode with automatic transition from PFM mode to fixed frequency PWM mode. This pin must be terminated.
PG Open-Drain PG: Power Good Open-Drain output. Connect an external pullup resistor to a rail which is below or equal AVIN.
PGND 1 PWR GND supply pin for the output stage.
PowerPAD™ — — For good thermal performance, this PAD must be soldered to the land pattern on the PCB. This PAD should be used as device GND.
PVIN 8 PWR VIN power supply pin for the output stage.
SW 2 O This is the switch pin and is connected to the internal MOSFET switches. Connect the external inductor between this terminal and the output capacitor.