JAJSE91A September   2017  – December 2017 TPS62097-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Terminal Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommend Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 100% Duty Cycle Mode
      2. 7.3.2 Switch Current Limit and Hiccup Short Circuit Protection
      3. 7.3.3 Under Voltage Lockout (UVLO)
      4. 7.3.4 Thermal Shutdown
    4. 7.4 Device Function Modes
      1. 7.4.1 Enable and Disable (EN)
      2. 7.4.2 Power Save Mode and Forced PWM Mode (MODE)
      3. 7.4.3 Soft Startup (SS/TR)
      4. 7.4.4 Voltage Tracking (SS/TR)
      5. 7.4.5 Power Good (PG)
  8. 8 Application Information
    1. 8.1 Application Information
    2. 8.2 1.8-V Output Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Output Voltage
        2. 8.2.2.2 Output Filter Design
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Capacitor Selection
      3. 8.2.3 Application Performance Curves
  9. 9 Power Supply Recommendations
  10. 10PCB Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Information
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGT|16
サーマルパッド・メカニカル・データ
発注情報

8 Application Information

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The following section discusses the design of the external components to complete the power supply design of the TPS62097-Q1.

8.2 1.8-V Output Application

TPS62097-Q1 TPS62097Q_typ.gif Figure 6. 1.8-V Output Application Schematic

8.2.1 Design Requirements

For this design example, use the following as the input parameters.

Table 3. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 2.5 V to 6 V
Output voltage 1.8 V
Output current 2.0 A

Table 4 lists the components used for the example.

Table 4. List of Components

REFERENCE DESCRIPTION MANUFACTURER(1)
C1 10 μF, Ceramic Capacitor, 6.3V, X7R, size 0805, C2012X7R0J106M125AB TDK
C2 22 μF, Ceramic Capacitor, 6.3V, X7S, size 0805, C2012X7S1A226M125AC TDK
C3 10 nF, Ceramic Capacitor, 6.3V, X7R, size 0603, GRM188R70J103KA01 Murata
L1 1 µH, Shielded, 5.4A, XFL4020-102MEB Coilcraft
R1 Depending on the output voltage, 1% accuracy Std
R2 20 kΩ, 1% accuracy Std
R3 100 kΩ, 1% accuracy Std

8.2.2 Detailed Design Procedure

8.2.2.1 Setting the Output Voltage

The output voltage is set by an external resistor divider according to the following equation:

Equation 4. TPS62097-Q1 EQ2_vout_lvsaw2.gif

R2 should not be higher than 20 kΩ to reduce noise coupling into the FB pin and improve the output voltage regulation. Choose additional resistor values for other outputs. A feed forward capacitor is not required.

The fixed output voltage version, TPS6209733-Q1, does not need an external resistor divider. TI recommends to connect the FB pin to AGND for improved thermal performance.

8.2.2.2 Output Filter Design

The inductor and the output capacitor together provide a low-pass filter. To simplify the selection process, Table 5 outlines possible inductor and capacitor value combinations for most applications.

Table 5. Output Capacitor / Inductor Combinations

NOMINAL L [µH](2) NOMINAL COUT [µF](3)
10 22 47 100 150
0.47
1 +(1) + + +
2.2
(1) Typical application configuration. Other '+' mark indicates recommended filter combinations. Other values may be acceptable in applications but should be fully tested by the user. Refer to the application note SLVA710.
(2) Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and -30%. The required effective inductance is 500nH minimum.
(3) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by 20% and -50%.

8.2.2.3 Inductor Selection

The main parameters for the inductor selection are the inductor value and the saturation current. To calculate the maximum inductor current under static load conditions, Equation 5 is given.

Equation 5. TPS62097-Q1 Eq_IL_peak_PWM_lvsae8.gif

Where:

IOUT,MAX = Maximum output current
ΔIL = Inductor current ripple
fSW = Switching frequency
L = Inductor value

TI recommends to choose the saturation current for the inductor 20% to 30% higher than the IL,MAX, out of Equation 5. A higher inductor value is also useful to lower ripple current but increases the transient response time as well.

8.2.2.4 Capacitor Selection

The input capacitor is the low impedance energy source for the converters which helps to provide stable operation. A low ESR multilayer ceramic capacitor is required for best filtering and should be placed between PVIN and PGND as close as possible to those pins. For most applications a 10-μF capacitor is sufficient, though a larger value reduces input current ripple.

The architecture of the TPS62097-Q1 allows the use of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends to use X7R or X5R dielectrics. The recommended typical output capacitor value is 22 μF and can vary over a wide range as outlined in Table 5.

Ceramic capacitors have a DC-Bias effect, which has a strong influence on the final effective capacitance. Choose the right capacitor carefully in combination with considering its package size and voltage rating. Ensure that the input effective capacitance is at least 5 μF and the output effective capacitance is at least 10 μF.

8.2.3 Application Performance Curves

TA = 25°C, BOM = Table 4 unless otherwise noted.

TPS62097-Q1 D001_SLVSDZ7_TPS62097Q.gif
VOUT = 1.0 V FSW = 2.0 MHz
Figure 7. Efficiency
TPS62097-Q1 D003_SLVSDZ7_TPS62097Q.gif
VOUT = 1.8 V FSW = 2.0 MHz
Figure 9. Efficiency
TPS62097-Q1 D005_SLVSDZ7_TPS62097Q.gif
VOUT = 3.3 V FSW = 2.0 MHz
Figure 11. Efficiency
TPS62097-Q1 D006_SLVSDZ7_TPS62097Q.gif
Figure 13. Load Regulation
TPS62097-Q1 D008_SLVSDZ7_TPS62097Q.gif
VOUT = 1.0 V RMode = 8.2 kΩ
Figure 15. Switching Frequency, Forced PWM Mode (1.5 MHz)
TPS62097-Q1 D010_SLVSDZ7_TPS62097Q.gif
VOUT = 1.0 V MODE = Open
Figure 17. Switching Frequency, Forced PWM Mode (2.5MHz)
TPS62097-Q1 D017_SLVSCD6_TPS62097.gif
VOUT = 1.2 V IOUT = 30 mA
Figure 19. Output Ripple, PSM Operation
TPS62097-Q1 D019_SLVSCD6_TPS62097.gif
VOUT = 1.2 V IOUT = 0 A to 2 A, 1A / µs
Figure 21. Load Transient, Forced PWM Mode (2.0MHz)
TPS62097-Q1 D021_SLVSCD6_TPS62097.gif
VOUT = 1.2 V ROUT = 0.6 Ω (2 A)
Figure 23. Startup and Shutdown with Load
TPS62097-Q1 D002_SLVSDZ7_TPS62097Q.gif
VOUT = 1.2 V FSW = 2.0 MHz
Figure 8. Efficiency
TPS62097-Q1 D004_SLVSDZ7_TPS62097Q.gif
VOUT = 2.5 V FSW = 2.0 MHz
Figure 10. Efficiency
TPS62097-Q1 D016_SLVSDZ7_TPS62097Q.gif
VOUT = 1.8 V VIN = 5.0 V
Figure 12. Efficiency with Different Switching Frequency
TPS62097-Q1 D007_SLVSDZ7_TPS62097Q.gif
Figure 14. Line Regulation
TPS62097-Q1 D009_SLVSDZ7_TPS62097Q.gif
VOUT = 1.0 V MODE = AGND, Forced PWM
Figure 16. Switching Frequency, Forced PWM Mode (2.0MHz)
TPS62097-Q1 D016_SLVSCD6_TPS62097.gif
VOUT = 1.2 V IOUT = 2 A
Figure 18. Output Ripple, PWM Operation (2.0MHz)
TPS62097-Q1 D018_SLVSCD6_TPS62097.gif
VOUT = 1.2 V IOUT = 0 A to 2 A, 1A / µs
Figure 20. Load Transient, PWM/PSM Mode (2.0MHz)
TPS62097-Q1 D020_SLVSCD6_TPS62097.gif
VOUT = 1.2 V ROUT = No Load
Figure 22. Startup and Shutdown without Load
TPS62097-Q1 D022_SLVSCD6_TPS62097.gif
VOUT = 1.2 V ROUT = 0.8 Ω (1.5 A) with 1-ms short
Figure 24. Short Circuit Protection, HICCUP