7.3.1 Pulse-Width Modulation (PWM) Operation

The TPS62152-Q1 device operates with pulse-width modulation in continuous conduction mode (CCM) with a nominal switching frequency of 2.5 MHz or 1.25 MHz, selectable with the FSW pin. The frequency variation in PWM is controlled and depends on V_IN, V_OUT and the inductance. The device operates in PWM mode as long the output current is higher than half the inductor ripple current. To maintain high efficiency at light loads, the device enters power-save mode at the boundary to discontinuous-conduction mode (DCM). This happens if the output current becomes smaller than half the inductor ripple current.

7.3.2 100% Duty-Cycle Operation

D = VOUT / VIN gives the duty cycle of the buck converter, which increases as the input voltage comes close to the output voltage. In this case, the device starts 100% duty-cycle operation, turning on the high-side switch 100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal set point. This allows the conversion of small input-to-output voltage differences, for example, for longest operation time of battery-powered applications. In 100% duty-cycle mode, the low-side FET switches off.

The calculation for minimum input voltage to maintain output voltage regulation, depending on the load current and the output voltage level, is:

Equation 1.

where

• I_OUT is the output current
• R_DS(on) is the on resistance of the high-side FET
• R_L is the DC resistance of the inductor used

7.3.3 Enable / Shutdown (EN)

Setting enable (EN) High starts operation of the device.

Pulling EN Low forces shutdown, with a shutdown current of typically 1.5 µA. The shutdown state turns off the internal power MOSFETs as well as the entire control circuitry. The internal resistive divider pulls down the output voltage smoothly. An internal pulldown resistor of about 400 kΩ is connected and keeps EN logic low, if the pin is floating. Driving the pin High disconnects the pulldown.

Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple power rails.

7.3.4 Soft Start or Tracking (SS/TR)

The internal soft-start circuitry controls the output voltage slope during start-up. This control avoids excessive inrush current, ensures a controlled output-voltage rise time, and prevents unwanted voltage drops from high-impedance power sources or batteries. On setting EN to start device operation, the device begins switching after a delay of about 50 µs and VOUT rises with a slope controlled by an external capacitor connected to the SS/TR pin. See Figure 21 and Figure 22 for typical start-up operation.

Connecting SS/TR directly to AVIN provides fastest start-up behavior. The TPS62152-Q1 device can start into a pre-biased output. During monotonic pre-biased start-up, neither power MOSFET turns on until the internal ramp of the device sets an output voltage above the pre-bias voltage. If EN = GND, setting the device to shutdown, or the device is in undervoltage lockout or thermal shutdown, an internal resistor pulls the SS/TR pin down to ensure a proper low level. Returning from those shutdown states causes a new start-up sequence as set by the SS/TR connection.

The device can track a master voltage supplied to SS/TR. The output voltage follows this voltage in both directions, up and down (see the Application Information section).

7.3.5 Current-Limit and Short-Circuit Protection

The TPS62152-Q1 device has protection against heavy loads and short-circuit events. At heavy loads, the current limit determines the maximum output current. On reaching the current limit, the high-side FET turns off. To avoid shoot-through current, the low-side FET switches on to sink the inductor current. The high-side FET turns on again only if the current in the low-side FET has decreased below the low-side current-limit threshold.

The current limit (see the Electrical Characteristics table) restricts the output current of the device. Because of internal propagation delay, the actual current can exceed the static current limit during this propagation delay time. The calculation for the dynamic current limit is as follows:

Equation 2.

where

• I_LIMF is the static current limit, specified in the Electrical Characteristics table
• V_L is the voltage across the inductor (V_IN – V_OUT)
• L is the inductor value
• t_PD is the internal propagation delay

The current limit can exceed static values, especially if the input voltage is high and the circuit uses very small inductances. The calculation for the peak current in the dynamic high-side switch is as follows:

Equation 3.

7.3.6 Power Good (PG)

The TPS62152-Q1 device has a built-in power-good (PG) function to indicate whether the output voltage has reached its appropriate level or not. One use of the PG signal is for start-up sequencing of multiple rails. The PG pin is an open-drain output that requires a pullup resistor to any voltage below 7 V. The pin can sink 2 mA of current and maintain its specified logic-low level. The pin is high-impedance when EN, UVLO, or thermal shutdown turns the device off. The TPS62152-Q1 device features PG = Low in this case and can be used to actively discharge VOUT. The V_IN voltage must remain present for the PG pin to stay Low.

7.3.7 Pin-Selectable Output Voltage (DEF)

Setting the DEF pin to High can increase the output voltage of the TPS62152-Q1 device by 5% above the nominal voltage (the maximum allowed voltage is 7 V; therefore, TI recommends connecting the DEF pin to VOUT or PG, not VIN). When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal voltage allows adapting the power supply voltage to the variations of the application hardware. See Voltage Margining Using the TPS62130, SLVA489, for detailed information on voltage margining using the TPS62152-Q1 device. A pulldown resistor of about 400 kΩ internally connects to the pin, to ensure a proper logic level if the pin is high-impedance or floating after initially set to Low. Setting the pin to High disconnects the resistor.

7.3.8 Frequency Selection (FSW)

To get high power density with a very small solution size, a high switching frequency allows the use of small external components for the output filter. However, switching losses increase with the switching frequency. If efficiency is the key parameter, more than solution size, set the switching frequency to half (1.25 MHz typical) by pulling FSW to High. It is mandatory to start with FSW = Low to limit inrush current. Connecting the pin to VOUT or PG is one way to ensure FSW = Low at start-up. Running with lower frequency achieves higher efficiency, but also creates higher output-voltage ripple. Pull FSW to Low for high frequency operation (2.5 MHz typical). To get low ripple and full output current at the lower switching frequency, TI recommends using an inductor of at least 2.2 µH. The device accommodates a change of switching frequency during operation, if needed. A pulldown resistor of about 400 kΩ internally connects to the pin, acting the same way as at the DEF pin (see Pin-Selectable Output Voltage (DEF)).

7.3.9 Undervoltage Lockout (UVLO)

If the input voltage drops, the undervoltage lockout prevents improper operation of the device by switching off both the power FETs. The typical setting of the undervoltage lockout threshold is 2.7 V. The device is fully operational for voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts operation again once the input voltage exceeds the threshold by a hysteresis of typically 200 mV.

7.3.10 Thermal Shutdown

An internal temperature sensor monitors the junction temperature (T_J) of the device. If T_J exceeds 160°C (typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs turn off, and PG goes into the high-impedance state. When T_J decreases below the hysteresis amount, the converter resumes normal operation, beginning with soft start. To avoid unstable conditions, the device implements a hysteresis of typically 20°C on the thermal shutdown temperature.

7.3.11 Tracking Function

For implementing a tracking function, use the SS/TR pin for this purpose by connecting it to an external tracking voltage. The output voltage tracks the external tracking voltage. If the tracking voltage is between 50 mV and
1.2 V, the FB pin tracks the SS/TR pin voltage as described in Equation 4 and shown in Figure 25.

Equation 4.

Figure 25. Voltage Tracking Relationship

When the SS/TR pin voltage reaches about 1.2 V, a clamp locks the internal voltage to the internal feedback voltage, and the device goes to normal regulation. This process works for rising and falling tracking voltages with the same behavior, as long as the input voltage is within the recommended operating conditions. For decreasing SS/TR pin voltage, the device does not sink current from the output. So, the resulting decrease of the output voltage may be slower than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin, which is V_IN + 0.3 V.

If the input voltage drops into undervoltage lockout or even down to zero, the output voltage goes to zero, independent of the tracking voltage. Figure 26 shows how to connect devices to get ratiometric and simultaneous sequencing by using the tracking function.

Figure 26. Sequence for Ratiometric and Simultaneous Start-Up

The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower, or the same as VOUT1.

To achieve a sequential start-up, connect the PG pin of VOUT1 to the EN pin of VOUT2. A ratiometric start-up sequence happens if both supplies share the same soft-start capacitor. Equation 10 calculates the soft-start time, though this circuit arrangement requires doubling the SS/TR current. See TPS62130/40/50 Sequencing and Tracking, SLVA470, for details about these and other tracking and sequencing circuits.

7.3.12 Feedback Pin (FB)

The FB pin is pulled down internally and may be left floating. Connecting to AGND to improve thermal resistance is recommended.

7.4.1 Power-Save Mode Operation

If the load current decreases, the TPS62152-Q1 device enters the built-in power-save mode seamlessly. This transition secures a high efficiency in light load operation. The device remains in power-save mode as long as the inductor current is discontinuous.

In power-save mode, the switching frequency decreases linearly with the load current, maintaining high efficiency. The transition into and out of power-save mode happens within the entire regulation scheme and is seamless in both directions.

The TPS62152-Q1 device includes a fixed on-time circuitry. The calculation for estimated on-time, in steady-state operation, is:

Equation 5.

For very small output voltages, the device keeps an absolute minimum on-time of about 80 ns to limit switching losses, thereby reducing the operating frequency from its nominal value, which keeps efficiency high. Use t_ON in Equation 6 to approximate the typical peak inductor current in power-save mode.

Equation 6.

When V_IN decreases to typically 15% above V_OUT, the TPS62152-Q1 device does not enter power-save mode, regardless of the load current. The device maintains output regulation in PWM mode.

7.4.2 Active Output Discharge

The TPS62152A-Q1 pulls the PG pin Low, when the device is shut down by EN, UVLO, or thermal shutdown. Connecting PG to VOUT through a resistor can be used to discharge VOUT in those cases (see Figure 27). The discharge rate can be adjusted by R_PG, which is also used to pull up the PG pin in normal operation. For reliability, keep the maximum current into the PG pin less than 10 mA.

Figure 27. Active Output Discharge Through PG Pin