SLVSA67F February 2010 – April 2020 TPS62400-Q1 , TPS62402-Q1 , TPS62404-Q1 , TPS62405-Q1
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
MIN | NOM | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
INTERFACE TIMING | |||||||
tStart | Start time | 2 | μs | ||||
tH_LB | High-time low bit, logic 0 detection | Signal level on MODE/DATA pin is > 1.2 V | 2 | 200 | μs | ||
tL_LB | Low-time low bit, logic 0 detection | Signal level on MODE/DATA pin < 0.4 V | 2 x tH_LB | 400 | μs | ||
tL_HB | Low-time high bit, logic 1 detection | Signal level on MODE/DATA pin < 0.4 V | 2 | 200 | μs | ||
tH_HB | High-time high bit, logic 1 detection | Signal level on MODE/DATA pin is > 1.2 V | 2 x tL_HB | 400 | μs | ||
tEOS | End of stream | 2 | μs | ||||
tACKN | Duration of acknowledge condition (MODE/DATE line pulled low by the device) | VIN 2.5 V to 6 V | 400 | 520 | μs | ||
tvalACK | Acknowledge valid time | 2 | μs | ||||
ttimeout | Time-out for entering power-save mode | MODE/DATA pin changes from high to low | 520 | μs |