JAJSF59E December   2014  – March 2022 TPS62406-Q1 , TPS62407-Q1 , TPS62422-Q1 , TPS62423-Q1 , TPS62424-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Converter 1
      2. 8.1.2 Converter 2
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable
      2. 8.3.2 DEF_1 Pin Function
      3. 8.3.3 180° Out-of-Phase Operation
      4. 8.3.4 Short-Circuit Protection
      5. 8.3.5 Thermal Shutdown
      6. 8.3.6 EasyScale Interface: One-Pin Serial Interface for Dynamic Output-Voltage Adjustment
        1. 8.3.6.1 General
        2. 8.3.6.2 Protocol
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Save Mode
        1. 8.4.1.1 Dynamic Voltage Positioning
        2. 8.4.1.2 Soft Start
        3. 8.4.1.3 100% Duty-Cycle Low-Dropout Operation
        4. 8.4.1.4 Undervoltage Lockout
      2. 8.4.2 Mode Selection
    5. 8.5 Programming
      1. 8.5.1 Addressable Registers
        1. 8.5.1.1 Bit Decoding
        2. 8.5.1.2 Acknowledge
        3. 8.5.1.3 Mode Selection
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Setting
          1. 9.2.2.1.1 Converter 1 Fixed Default Output-Voltage Setting
          2. 9.2.2.1.2 Converter 2 Fixed Default Output-Voltage Setting
        2. 9.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Output-Capacitor Selection
          3. 9.2.2.2.3 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 サポート・リソース
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

VIN = 3.6 V, EN1 = EN2 = VIN, MODE = GND, L1 = L2 = 2.2 μH, COUT1 = COUT2 = 20 μF, TJ = –40°C to 125°C, typical values are at TJ = 25°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY CURRENT
VINInput voltage range2.56V
IQOperating quiescent currentOne converter, no load on the output. PFM mode enabled (MODE/DATA = GND) device not switching,
EN1 = 1 or EN2 = 1		1935μA
Two converters, no load on the output. PFM mode enabled (MODE/DATA = GND) device not switching,
EN1 = EN2 = 1		3250
No load on the output, MODE/DATA = GND, for one converter(1)23
No load on the output, MODE/DATA = VIN, for one converter(1)3.6mA
ISDShutdown currentEN1, EN2 = GND, VIN = 3.6 V(2)1.23μA
EN1, EN2 = GND, VIN ramped from 0 V to 3.6 V(3)0.11.5
VUVLOUndervoltage lockout thresholdFalling1.52.35V
Rising2.4
ENABLE EN1, EN2
VIHHigh-level input voltage range, EN1, EN21.2VINV
VILLow-level input voltage range, EN1, EN200.4V
IINInput bias current, EN1, EN2EN1, EN2 = GND or VIN0.051μA
DEF_1 INPUT
VDEF_1HDEF_1 high-level digital input voltage range0.9VINV
VDEF_1LDEF_1 low-level digital input voltage range00.4V
IINInput bias current DEF_1DEF_1 = GND or VIN0.011μA
MODE/DATA
VIHHigh-level input voltage range, MODE/DATA1.2VINV
VILLow-level input voltage range, MODE/DATA00.4V
IINInput bias current, MODE/DATAMODE/DATA = GND or VIN0.011μA
VOHAcknowledge output voltage highOpen drain, through external pullup resistorVINV
VOLAcknowledge output voltage lowOpen drain, sink current 500 μA00.4V
POWER SWITCH
rDS(on)P-channel MOSFET on-resistance, converter 1 and 2VIN = VGS = 3.6 V280620mΩ
ILK_PMOSP-channel leakage currentVDS = 6 V1μA
rDS(on)N-channel MOSFET on-resistance converter 1 and 2VIN = VGS = 3.6 V200450mΩ
ILK_SW1/SW2Leakage current into SW1 or SW2 pinIncludes N-channel leakage current,
VIN = open, VSW = 6 V, EN = GND(4)		67.5μA
ILIMFForward current limit PMOS and NMOSTPS62406-Q1 VOUT12.5 V ≤ VIN ≤ 6 V1.181.41.61A
TPS62406-Q1 VOUT22.5 V ≤ VIN ≤ 6 V0.680.80.92
TPS62407-Q1 VOUT12.5 V ≤ VIN ≤ 6 V0.680.80.92
TPS62407-Q1 VOUT22.5 V ≤ VIN ≤ 6 V0.7511.15
TPS62422-Q1 VOUT12.5 V ≤ VIN ≤ 6 V1.181.41.61
TPS62422-Q1 VOUT22.5 V ≤ VIN ≤ 6 V0.7511.15
TPS62423-Q1 VOUT12.5 V ≤ VIN ≤ 6 V11.21.38
TPS62423-Q1 VOUT22.5 V ≤ VIN ≤ 6 V11.21.38
TPS62424-Q1 VOUT12.5 V ≤ VIN ≤ 6 V11.21.38
TPS62424-Q1 VOUT22.5 V ≤ VIN ≤ 6 V11.21.38
TSDThermal shutdownIncreasing junction temperature150°C
Thermal shutdown hysteresisDecreasing junction temperature20°C
OUTPUT
VrefInternal Reference voltage600mV
VOUTx(PFM)DC output voltage accuracyVoltage positioning active,
MODE/DATA = GND,
device operating in PFM mode,
VIN = 2.5 V to 5 V(5)(6)		–1.5%1%2.5%
VOUTx(PWM)MODE/DATA = GND;
device operating in PWM mode,
VIN = 2.5 V to 6 V(6)		–1%0%1%
VIN = 2.5 V to 6 V, MODE/DATA = VIN,
Fixed PWM operation,
0 mA < IOUT1 < 400 mA ; 0 mA < IOUT2 < 600 mA(7)		–1%0%1%
DC output voltage load regulationPWM operation mode0.5%/A
(1) Device is switching with no load on the output, L1 = L2 = 3.3 μH, value includes losses of the coil.
(2) These values are valid after enabling the device one time (EN1 or EN2 = high) and maintaining supply voltage VIN.
(3) These values are valid when the device is disabled (EN1 and EN2 low) and supply voltage VIN is powered up. The values remain valid until enabling the device the first time (EN1 or EN2 = high). After the first enable, Note 3 becomes valid.
(4) An internal resistor of 1 MΩ connects pins SW1 and SW2 to GND.
(5) Configuration L1 or L2 typ. 2.2 μH, COUTx typ 20 μF. See parameter measurement information, the output voltage ripple in PFM mode depends on the effective capacitance of the output capacitor; larger output capacitors lead to tighter output voltage tolerance.
(6) In power-save mode, the device typically enters PWM operation at IPSM = VIN / 32 Ω.
(7) For VOUTx > 2 V, VIN min = VOUTx + 0.5 V