JAJSJS5B March   2021  – April 2024 TPS628501 , TPS628502 , TPS628503

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Schematic
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Precise Enable (EN)
      2. 8.3.2 COMP/FSET
      3. 8.3.3 MODE / SYNC
      4. 8.3.4 Spread Spectrum Clocking (SSC)
      5. 8.3.5 Undervoltage Lockout (UVLO)
      6. 8.3.6 Power Good Output (PG)
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode Operation (PWM/PFM)
      3. 8.4.3 100% Duty-Cycle Operation
      4. 8.4.4 Current Limit and Short Circuit Protection
      5. 8.4.5 Foldback Current Limit and Short Circuit Protection
      6. 8.4.6 Output Discharge
      7. 8.4.7 Soft Start
      8. 8.4.8 Input Overvoltage Protection
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Programming the Output Voltage
      2. 9.1.2 Inductor Selection
      3. 9.1.3 Capacitor Selection
        1. 9.1.3.1 Input Capacitor
        2. 9.1.3.2 Output Capacitor
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Synchronizing to an External Clock
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.2 COMP/FSET

This pin allows to set three different parameters:

  • Internal compensation settings for the control loop (two settings available)
  • The switching frequency in PWM mode from 1.8 MHz to 4 MHz
  • Enable/disable spread spectrum clocking (SSC)

A resistor from COMP/FSET to GND changes the compensation as well as the switching frequency. The change in compensation allows the user to adopt the device to different values of output capacitance. The resistor must be placed close to the pin to keep the parasitic capacitance on the pin to a minimum. The compensation setting is sampled at start-up of the converter, so a change in the resistor during operation only has an effect on the switching frequency but not on the compensation.

To save external components, the pin can also be directly tied to VIN or GND to set a pre-defined setting. Do not leave the pin floating.

The switching frequency has to be selected based on the input voltage and the output voltage to meet the specifications for the minimum on-time and minimum off-time.

Example: VIN = 5 V, VOUT = 0.6 V --> duty cycle = 0.6 V / 5 V = 0.12

  • --> ton,min = 1 / fs × 0.12
  • --> fsw,max = 1 / ton,min × 0.12 = 1 / 0.05 µs × 0.12 = 2.4 MHz

The compensation range has to be chosen based on the minimum capacitance used. The capacitance can be increased from the minimum value as given in Table 8-1, up to the maximum of 200 µF in both compensation ranges. If the capacitance of an output changes during operation, for example, when load switches are used to connect or disconnect parts of the circuitry, the compensation has to be chosen for the minimum capacitance on the output. With large output capacitance, the compensation must be done based on that large capacitance to get the best load transient response. Compensating for large output capacitance but placing less capacitance on the output can lead to instability.

The switching frequency for the different compensation setting is determined by the following equations.

For compensation (comp) setting 1 with spread spectrum clocking (SSC) disabled:

Equation 1. GUID-9336B99D-9FA8-4978-8E2B-D6B3D04354BB-low.gif

For compensation (comp) setting 1 with spread spectrum clocking (SSC) enabled:

Equation 2. GUID-619339EB-913E-40A3-9A10-CD0B737188A6-low.gif

For compensation (comp) setting 2 with spread spectrum clocking (SSC) disabled:

Equation 3. GUID-0857CE7D-A2AE-4BFB-9673-64FC10B5B0AE-low.gif
Table 8-1 Switching Frequency, Compensation and Spread Spectrum Clocking
RCFCOMPENSATIONSWITCHING FREQUENCYMINIMUM OUTPUT CAPACITANCE
FOR VOUT < 1 V		MINIMUM OUTPUT CAPACITANCE
FOR 1 V ≤ VOUT < 3.3 V		MINIMUM OUTPUT CAPACITANCE
FOR VOUT ≥ 3.3 V
10 kΩ .. 4.5 kΩfor smallest output capacitance
(comp setting 1)
SSC disabled		1.8 MHz (10 kΩ) .. 4 MHz (4.5 kΩ)
according to Equation 1		15 µF10 µF8 µF
33 kΩ .. 15 kΩfor smallest output capacitance
(comp setting 1)
SSC enabled		1.8 MHz (33 kΩ) .. 4 MHz (15 kΩ)
according to Equation 2		15 µF10 µF8 µF
100 kΩ .. 45 kΩfor best transient response (larger output capacitance)
(comp setting 2)
SSC disabled		1.8 MHz (100 kΩ) ..4 MHz (45 kΩ)
according to Equation 3		30 µF18 µF15 µF
tied to GNDfor smallest output capacitance
(comp setting 1)
SSC disabled		internally fixed 2.25 MHz15 µF10 µF8 µF
tied to VINfor best transient response (larger output capacitance)
(comp setting 2)
SSC enabled		internally fixed 2.25 MHz30 µF18 µF15 µF

Refer to Section 9.1.3.2 for further details on the output capacitance required depending on the output voltage.

A resistor value that is too high for RCF is decoded as "tied to VIN". A value below the lowest range is decoded as "tied to GND". The minimum output capacitance in Table 8-1 is for capacitors close to the output of the device. If the capacitance is distributed, a lower compensation setting can be required.