JAJSLY4B January   2023  – May 2024 TPS62870 , TPS62871 , TPS62872 , TPS62873

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Device Options
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings_Catalog
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing Characteristics
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed-Frequency DCS Control Topology
      2. 8.3.2  Forced PWM and Power Save Modes
      3. 8.3.3  Precise Enable
      4. 8.3.4  Start-Up
      5. 8.3.5  Switching Frequency Selection
      6. 8.3.6  Output Voltage Setting
        1. 8.3.6.1 Output Voltage Range
        2. 8.3.6.2 Output Voltage Setpoint
        3. 8.3.6.3 Non-Default Output Voltage Setpoint
        4. 8.3.6.4 Dynamic Voltage Scaling
      7. 8.3.7  Compensation (COMP)
      8. 8.3.8  Mode Selection and Clock Synchronization (MODE/SYNC)
      9. 8.3.9  Spread Spectrum Clocking (SSC)
      10. 8.3.10 Output Discharge
      11. 8.3.11 Undervoltage Lockout (UVLO)
      12. 8.3.12 Overvoltage Lockout (OVLO)
      13. 8.3.13 Overcurrent Protection
        1. 8.3.13.1 Cycle-by-Cycle Current Limiting
        2. 8.3.13.2 Hiccup Mode
        3. 8.3.13.3 Current Limit Mode
      14. 8.3.14 Power Good (PG)
        1. 8.3.14.1 Standalone or Primary Device Behavior
        2. 8.3.14.2 Secondary Device Behavior
      15. 8.3.15 Remote Sense
      16. 8.3.16 Thermal Warning and Shutdown
      17. 8.3.17 Stacked Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Undervoltage Lockout
      3. 8.4.3 Standby
      4. 8.4.4 On
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard, Fast, Fast Mode Plus Protocol
      3. 8.5.3 I2C Update Sequence
      4. 8.5.4 I2C Register Reset
  10. 9 Register Map
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Selecting the Inductor
        2. 10.2.2.2 Selecting the Input Capacitors
        3. 10.2.2.3 Selecting the Compensation Resistor
        4. 10.2.2.4 Selecting the Output Capacitors
        5. 10.2.2.5 Selecting the Compensation Capacitor, CC
        6. 10.2.2.6 Selecting the Compensation Capacitor, CC2
      3. 10.2.3 Application Curves
    3. 10.3 Best Design Practices
    4. 10.4 Power Supply Recommendations
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating junction temperature (TJ = –40 °C to 125 °C) and VIN = 2.7 V to 6 V. Typical values at VIN = 3.3 V and TJ = 25 °C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Supply current (VIN) Operating EN = high, IOUT = 0 mA, V(SW) = 0 V, primary operation, device not switching, TJ = 25 °C 1.75 3 mA
Standby EN = low, V(SW) = 0 V, TJ = 25 °C 16.5 40 µA
VIT+ Positive-going UVLO threshold voltage (VIN) 2.5 2.6 2.7 V
VIT– Negative-going UVLO threshold voltage (VIN) 2.4 2.5 2.6 V
Vhys UVLO hysteresis voltage (VIN) 90 mV
VIT+ Positive-going OVLO threshold voltage (VIN) 6.1 6.3 6.5 V
VIT– Negative-going OVLO threshold voltage (VIN) 6.0 6.2 6.4 V
Vhys OVLO hysteresis voltage (VIN) 85 mV
VIT– Negative-going power-on reset threshold 1.4 V
TSD Thermal shutdown threshold temperature TJ rising 170 °C
Thermal shutdown hysteresis 20 °C
TW Thermal warning threshold temperature TJ rising 150 °C
Thermal warning hysteresis 20 °C
CONTROL and INTERFACE
VIT+ Positive-going input threshold voltage (EN) 0.97 1.0 1.03 V
VIT– Negative-going input threshold voltage (EN) 0.87 0.9 0.93 V
Vhys Hysteresis voltage (EN) 95 mV
IIH High-level input current (EN) VIH = VIN, internal pulldown resistor disabled 200 nA
IIL Low-level input current (EN) VIL = 0 V, internal pulldown resistor disabled –200 nA
VIH High-level input voltage (SDA, SCL, MODE/SYNC, VSEL, FSEL, SYNC_OUT) 0.8 V
VIL Low-level input voltage (SDA, SCL, MODE/SYNC, VSEL, FSEL, SYNC_OUT) 0.4 V
VOL Low-level output voltage (SDA) IOL = 3 mA 0.4 V
IOL = 9 mA 0.4 V
IOL = 5 mA 0.2 V
IOH High-level output current (SDA, SCL) VOH = 3.3 V 200 nA
IIL Low-level input current (MODE/SYNC) VIL = 0 V –150 150 nA
IIH High-level input current (MODE/SYNC) VIH = VIN 3 µA
IIL Low-level input current (SYNC_OUT) VIL = 0 V –250 nA
IIH High-level input current (SYNC_OUT) VIH = 2 V 150 nA
td(EN)1 Enable delay time when EN tied to VIN Measured from when EN goes high to when device starts switching
SRVIN = 1 V/µs		 175 500 µs
td(EN)2 Enable delay time when VIN already applied Measured from when EN goes high to when device starts switching 100 µs
td(RAMP) Output voltage ramp time Measured from when device starts switching to rising edge of PG 0.35 0.5 0.65 ms
0.7 1 1.3 ms
1.4 2 2.6 ms
2.8 4 5.2 ms
Time to lock external frequency 50 µs
Internal pullup resistance (VSEL, FSEL) 5.5 9 kΩ
Internal pulldown resistance (VSEL, FSEL) 1.3 2.2 kΩ
VT+ Positive-going power good threshold voltage (output undervoltage) 94 96 98 %VOUT
VT– Negative-going power good threshold voltage (output undervoltage) 92 94 96 %VOUT
VT+ Positive-going power good threshold voltage (output overvoltage) 104 106 108 %VOUT
VT– Negative-going power good threshold voltage (output overvoltage) 102 104 106 %VOUT
VOL Low-level output voltage (PG) IOL = 1 mA 0.3 V
IOH High-level output current (PG) VOH = 3.3 V 200 nA
VIH High-level input voltage (PG) Device configured as a secondary device in stacked operation 0.8 V
VIL Low-level input voltage (PG) Device configured as a secondary device in stacked operation 0.4 V
IIH High-level input current (PG) Device configured as a secondary device in stacked operation 1 µA
IIL Low-level input current (PG) Device configured as a secondary device in stacked operation –1 µA
td(PG) Deglitch time (PG) High-to-low or low-to-high transition on the PG pin 34 40 46 µs
OUTPUT
VOUT Output accuracy VIN ≥ VOUT + 1.4 V –1 1 %
IIB Input bias current (GOSNS) V(GOSNS) = –100 mV to 100 mV –6 µA
IIB Input bias current (VOSNS) V(VOSNS) = 3.3 V, VIN = 6 V 6 µA
VICR Input common-mode range (GOSNS) –100 100 mV
Output discharge current in constant current mode V(VOSNS) = 2 V 50 115 200 mA
RDIS Output discharge resistance in resistive discharge mode V(VOSNS) ≤ 0.5 V 6 Ω
fSW Switching frequency (SW) fSW = 1.5 MHz, PWM operation, VIN 3.3 V, VOUT = 0.75 V 1.35 1.5 1.65 MHz
fSW = 2.25 MHz, PWM operation, VIN 3.3 V, VOUT = 0.75 V 2.025 2.25 2.475
fSW = 2.5 MHz, PWM operation, VIN 3.3 V, VOUT = 0.75 V 2.25 2.5 2.75
fSW = 3 MHz, PWM operation, VIN 3.3 V, VOUT = 0.75 V 2.7 3 3.3
fmod Frequency of the spread-spectrum sweep fsw/2048 kHz
ΔfSW Switching frequency variation during spread-spectrum operation ±10%
τ Emulated current time constant 12.5 µs
rDS(on) High-side FET static on-state resistance VIN = 3.3 V 7 16 mΩ
rDS(on) Low-side FET static on-state resistance VIN = 3.3 V 4.1 9.4 mΩ
I(SW)(off) High-side FET off-state current VIN = 6 V, V(SW) = 0 V, TJ = 25 °C –1 µA
Low-side FET off-state current VIN = 6 V, V(SW) = 6 V, TJ = 25 °C 100
ILIM High-side FET forward switch current limit, DC TPS62870 9 12 14 A
TPS62871 12 16 18
TPS62872 15 20 22
TPS62873 18 24 26
Low-side FET negative current limit, DC 7.5 12 A