JAJSMG2C November   2023  – October 2024 TPS6287B10 , TPS6287B15 , TPS6287B20 , TPS6287B25 , TPS6287B30

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed-Frequency DCS-Control Topology
      2. 8.3.2  Forced-PWM and Power-Save Modes
      3. 8.3.3  Transient Non-Synchronous Mode (optional)
      4. 8.3.4  Precise Enable
      5. 8.3.5  Start-Up
      6. 8.3.6  Switching Frequency Selection, Only Applies to TPS6287BxxJE2
      7. 8.3.7  Output Voltage Setting
        1. 8.3.7.1 Output Voltage Range
        2. 8.3.7.2 Output Voltage Setpoint
        3. 8.3.7.3 Non-Default Output Voltage Setpoint
        4. 8.3.7.4 Dynamic Voltage Scaling
        5. 8.3.7.5 Droop Compensation
      8. 8.3.8  Compensation (COMP)
      9. 8.3.9  Mode Selection / Clock Synchronization (MODE/SYNC)
      10. 8.3.10 Spread Spectrum Clocking (SSC)
      11. 8.3.11 Output Discharge
      12. 8.3.12 Undervoltage Lockout (UVLO)
      13. 8.3.13 Overvoltage Lockout (OVLO)
      14. 8.3.14 Overcurrent Protection
        1. 8.3.14.1 Cycle-by-Cycle Current Limiting
        2. 8.3.14.2 Hiccup Mode
        3. 8.3.14.3 Current-Limit Mode
      15. 8.3.15 Power Good (PG)
        1. 8.3.15.1 Standalone, Primary Device Behavior
        2. 8.3.15.2 Secondary Device Behavior
      16. 8.3.16 Remote Sense
      17. 8.3.17 Thermal Warning and Shutdown
      18. 8.3.18 Stacked Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Undervoltage Lockout
      3. 8.4.3 Standby
      4. 8.4.4 On
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 8.5.3 HS-Mode Protocol
      4. 8.5.4 I2C Update Sequence
      5. 8.5.5 I2C Register Reset
      6. 8.5.6 Dynamic Voltage Scaling (DVS)
  10. 9 Device Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Selecting the Input Capacitors
        3. 10.2.2.3 Selecting the Compensation Resistor
        4. 10.2.2.4 Selecting the Output Capacitors
        5. 10.2.2.5 Selecting the Compensation Capacitor CC
        6. 10.2.2.6 Selecting the Compensation Capacitor CC2
      3. 10.2.3 Application Curves
    3. 10.3 Typical Application - TPS6287BxV Devices
      1. 10.3.1 Design Requirements for TPS6287BxV
    4. 10.4 Typical Application Using Two TPS6287B25 in a Stacked Configuration
      1. 10.4.1 Design Requirements For Two Stacked Devices
      2. 10.4.2 Detailed Design Procedure
        1. 10.4.2.1 Selecting the Compensation Resistor
        2. 10.4.2.2 Selecting the Output Capacitors
        3. 10.4.2.3 Selecting the Compensation Capacitor CC
      3. 10.4.3 Application Curves for Two Stacked Devices
    5. 10.5 Typical Application Using Three TPS6287B25 in a Stacked Configuration
      1. 10.5.1 Application Curves
    6. 10.6 Power Supply Recommendations
    7. 10.7 Layout
      1. 10.7.1 Layout Guidelines
      2. 10.7.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.18 Stacked Operation

Connect multiple TPS6287Bx devices in parallel in what is known as a "stack"; for example, to increase output current capability or reduce device junction temperature. A stack comprises one primary device and one or more secondary devices. During initialization, each device monitors the SYNCOUT pin to determine if it must operate as a primary device or a secondary device:

  • If there is a 47kΩ resistor between the SYNCOUT pin and ground, the device operates as a secondary device
  • If the SYNCOUT pin is high impedance, the device operates as a primary device

Figure 8-16 shows the recommended interconnections in a stack of two TPS6287Bx devices.

TPS6287B10 TPS6287B15 TPS6287B20 TPS6287B25 TPS6287B30 Two TPS6287Bx Devices in a Stacked Configuration Figure 8-16 Two TPS6287Bx Devices in a Stacked Configuration
The key points to note are:

  • All the devices in the stack share a common enable signal, which must be pulled up with a resistance of at least 15kΩ.
  • All the devices in the stack share a common power-good signal.
  • All the devices in the stack share a common compensation signal.
  • All secondary devices must connect a 47kΩ resistor between the SYNC_OUT pin and ground.
  • The remote sense pins (VOSNS and GOSNS) of each device must be connected (do not leave these pins floating).
  • VOSNS and GOSNS of the primary device must be connected to the capacitor at the load
  • VOSNS and GOSNS of the secondary devices can either be connected to the output capacitor at the device or alternatively both pins can be tied to AGND.
  • The primary device must be configured for forced-PWM operation (secondary devices are automatically configured for forced-PWM operation).
  • A stacked configuration can support synchronization to an external clock or spread-spectrum clocking.
  • Only the VSET1 and VSET2 pins of the primary device is used to set the default output voltage. The VSET1 and VSET2 pins of secondary devices is not used and must be connected to ground.
  • The SDA and SCL pins of secondary devices are not used and must be connected to ground.
  • A stacked configuration uses a daisy-chained clocking signal, in which each device switches with a phase offset of approximately 120° relative to the adjacent devices in the daisy-chain. To daisy-chain the clocking signal, connect the SYNCOUT pin of the primary device to the MODE/SYNC pin of the first secondary device. Connect the SYNCOUT pin of the first secondary device to the MODE/SYNC pin of the second secondary device. Continue this connection scheme for all devices in the stack, to daisy-chain them together.

  • CONTROL2:SYNC_OUT_PHASE = 1 sets a phase shift of 180° from the primary to the first secondary device. Please see the DEVICE OPTIONS table for the complete list of available OTP spins.

  • Hiccup overcurrent protection must not be used in a stacked configuration.

In a stacked configuration, the common enable signal also acts as a SYSTEM_READY signal (see Section 8.3.4). Each device in the stack can pull the EN pin low during device start-up or when a fault occurs. Thus, the stack is only enabled when all devices have completed the start-up sequence and are fault-free. A fault in any one device disables the whole stack for as long as the fault condition exists.

During start-up, the primary device pulls the COMP pin low for as long as the enable signal (SYSTEM_READY) is low. When the enable signal goes high, the primary device actively controls the COMP pin and all devices in the stack follow the COMP voltage. During start-up, each device in the stack pulls the PG pin low while the pin initializes. When initialization is complete, each secondary device in the stack sets the PG pin to a high impedance and the primary device alone controls the state of the PG signal. The PG pin goes high when the stack has completed the start-up ramp and the output voltage is within specification. The secondary devices in the stack detect the rising edge of the power-good signal and switch from DCM operation to CCM operation. After the stack has successfully started up, the primary device controls the power-good signal in the normal way. In a stacked configuration, there are some faults that only affect individual devices, and other faults that affect all devices. For example, if one device enters current limit, only that device is affected. But a thermal shutdown or undervoltage lockout event in one device disables all devices through the shared enable (SYSTEM_READY) signal.

Functionality During Stacked Operation

Some device features are not available during stacked operation, or are only available in the primary converter. Table 8-11 summarizes the available functionality during stacked operation.

Table 8-11 Functionality During Stacked Operation
FunctionPrimary DeviceSecondary DeviceRemark
UVLOYes

Yes

Common enable signal
OVLOYes

Yes

Common enable signal
OCP – Current LimitYesYesIndividual
OCP – Hiccup OCPNoNoDo not use during stacked operation
Thermal ShutdownYesYesCommon enable signal
Power-Good (Window Comparator)YesNoPrimary device only
I2C InterfaceYesNoPrimary device only
DVSVia I2CNoVoltage loop controlled by primary device only
SSCVia I2CNoDaisy-chained from primary device to secondary devices
SYNCYesYesSynchronization clock applied to primary device
Precise EnableNoNoOnly binary enable
Output DischargeYesYesAlways enabled in secondary devices

Fault Handling During Stacked Operation

In a stacked configuration, there are some faults that only affect individual devices, and other faults that affect all devices. For example, if one device enters current limit, only that device is affected. But a thermal shutdown or undervoltage lockout event in one device disables all devices via the shared enable (SYSTEM_READY) signal. Table 8-12 summarizes the fault handling of the TPS6287Bx devices during stacked operation.

Table 8-12 Fault Handling During Stacked Operation
Fault ConditionDevice ResponseSystem Response
UVLOEnable signal pulled lowNew soft start
OVLO
Thermal Shutdown
Current LimitEnable signal remains highError amplifier clamped

External CLK applied to MODE/SYNC fails

SYNC_OUT and power-stage switch to internal oscillator

System active but switching frequency is not synchronized if clk to a secondary device fails