JAJSQH7 june   2023 TPS62901-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Mode Selection and Device Configuration MODE/S-CONF
      2. 8.3.2  Adjustable VO Operation (External Voltage Divider)
      3. 8.3.3  Selectable VO Operation (VSET and Internal Voltage Divider)
      4. 8.3.4  Soft Start and Tracking (SS/TR)
        1. 8.3.4.1 Tracking Function
      5. 8.3.5  Smart Enable with Precise Threshold
      6. 8.3.6  Power Good (PG)
      7. 8.3.7  Output Discharge Function
      8. 8.3.8  Undervoltage Lockout (UVLO)
      9. 8.3.9  Current Limit and Short-Circuit Protection
      10. 8.3.10 High Temperature Specifications
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced Pulse Width Modulation (FPWM) Operation
      2. 8.4.2 Power Save Mode Operation (Auto PFM and PWM)
      3. 8.4.3 AEE (Automatic Efficiency Enhancement)
      4. 8.4.4 100% Duty-Cycle Operation
      5. 8.4.5 Starting into a Prebiased Load
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application with Adjustable Output Voltage
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Programming the Output Voltage
        3. 9.2.2.3 External Component Selection
          1. 9.2.2.3.1 Output Filter and Loop Stability
          2. 9.2.2.3.2 Inductor Selection
          3. 9.2.2.3.3 Capacitor Selection
            1. 9.2.2.3.3.1 Output Capacitor
            2. 9.2.2.3.3.2 Input Capacitor
            3. 9.2.2.3.3.3 Soft-Start Capacitor
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Application Curves Vout = 1.8 V
        2. 9.2.3.2 Application Curves Vout = 1.2 V
        3. 9.2.3.3 Application Curves Vout = 0.6 V
    3. 9.3 Typical Application with Selectable VOUT using VSET
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Programming the Output Voltage
      3. 9.3.3 Application Curves
        1. 9.3.3.1 Application Curves Vout = 5 V
        2. 9.3.3.2 Application Curves Vout = 3.3 V
    4. 9.4 System Examples
      1. 9.4.1 LED Power Supply
      2. 9.4.2 Powering Multiple Loads
      3. 9.4.3 Voltage Tracking
      4. 9.4.4 Inverting Buck-Boost (IBB)
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
      3. 9.6.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.3 Selectable VO Operation (VSET and Internal Voltage Divider)

If the device is configured to VSET operation, VO is sensed only through the VOS pin by an internal resistor divider. The target VO is programmed by an external resistor (RVSET) connected between the VSET pin and GND. Figure 8-3 shows the typical schematic for this configuration.

CAUTION: The MODE/S-CONF pin must not be configured for external feedback operation (see Table 8-1) if only RVSET (R2 as shown in Figure 8-3) is populated. This causes the output voltage to become unregulated and can damage to the device or surrounding circuitry.
GUID-20230329-SS0I-2C3V-NTN2-DGF8RPCH8PFV-low.svg Figure 8-3 Selectable VO Operation Schematic
Table 8-2 VSET Selection Table
# Level Or Resistor Value [Ω] (1) Target VO [V]
1 GND 1.2
2 4.64 k 0.4
3 5.76 k 0.6
4 7.15 k 0.8
5 8.87 k 1.0
6 11.0 k 1.1
7 13.7 k 1.3
8 16.9 k 1.35
9 21.0 k 1.8
10 26.1 k 1.9
11 40.2 k 2.5
12 61.9 k 3.8
13 76.8 k 5.0
14 95.3 k 1.25
15 118.0 k 5.5
16 249.00 k or larger/Open 3.3
(1) E96 resistor series, 1% accuracy, temperature coefficient better or equal than ±200 ppm/°C