JAJSM97D June   2021  – August 2022 TPS62932 , TPS62933 , TPS62933F , TPS62933O , TPS62933P

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Fixed Frequency Peak Current Mode
      2. 9.3.2  Pulse Frequency Modulation
      3. 9.3.3  Voltage Reference
      4. 9.3.4  Output Voltage Setting
      5. 9.3.5  Switching Frequency Selection
      6. 9.3.6  Enable and Adjusting Undervoltage Lockout
      7. 9.3.7  External Soft Start and Prebiased Soft Start
      8. 9.3.8  Power Good
      9. 9.3.9  Minimum On Time, Minimum Off Time, and Frequency Foldback
      10. 9.3.10 Frequency Spread Spectrum
      11. 9.3.11 Overvoltage Protection
      12. 9.3.12 Overcurrent and Undervoltage Protection
      13. 9.3.13 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Modes Overview
      2. 9.4.2 Heavy Load Operation
      3. 9.4.3 Light Load Operation
      4. 9.4.4 Out of Audio Operation
      5. 9.4.5 Forced Continuous Conduction Operation
      6. 9.4.6 Dropout Operation
      7. 9.4.7 Minimum On-Time Operation
      8. 9.4.8 Shutdown Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Custom Design With WEBENCH® Tools
        2. 10.2.2.2  Output Voltage Resistors Selection
        3. 10.2.2.3  Choosing Switching Frequency
        4. 10.2.2.4  Soft-Start Capacitor Selection
        5. 10.2.2.5  Bootstrap Capacitor Selection
        6. 10.2.2.6  Undervoltage Lockout Setpoint
        7. 10.2.2.7  Output Inductor Selection
        8. 10.2.2.8  Output Capacitor Selection
        9. 10.2.2.9  Input Capacitor Selection
        10. 10.2.2.10 Feedforward Capacitor CFF Selection
        11. 10.2.2.11 Maximum Ambient Temperature
      3. 10.2.3 Application Curves
    3. 10.3 What to Do and What Not to Do
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
        1. 13.1.2.1 Custom Design With WEBENCH® Tools
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Electrical Characteristics

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of the product containing it. TJ = –40°C to +150°C, VIN = 3.8 V to 30 V, unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLY (VIN PIN)
VINOperation input voltage3.830V
IQNonswitching quiescent currentEN = 5 V, VFB = 0.85 V, TPS62932, TPS62933, and TPS62933P 12µA
EN = 5 V, VFB = 1 V, TPS62933F 125
EN = 5 V, VFB = 1 V, TPS62933O 45
ISHDNShutdown supply currentVEN = 0 V2µA
VIN_UVLOInput undervoltage lockout thresholdsRising threshold3.43.63.8V
Falling threshold3.13.33.5V
Hysteresis300mV
ENABLE (EN PIN)
VEN_RISEEnable thresholdRising enable threshold1.211.28V
VEN_FALL

Disable threshold

Falling disable threshold1.11.17V
IpEN pullup currentVEN = 1.0 V0.7µA
IhEN pullup hysteresis currentVEN = 1.5 V1.4µA
VOLTAGE REFERENCE (FB PIN)
VFBFB voltageTJ = 25°C792800808mV
TJ = 0°C to 85°C788800812mV
TJ = –40°C to 150°C784800816mV
IFBInput leakage currentVFB = 0.8 V0.15μA
INTEGRATED POWER MOSFETS
RDSON_HSHigh-side MOSFET on-resistanceTJ = 25°C, VBST – SW = 5 V 76mΩ
RDSON_LSLow-side MOSFET on-resistanceTJ = 25°C 32mΩ
CURRENT LIMIT
IHS_LIMITHigh-side MOSFET current limitTPS62933 and TPS62933x4.255.8A
TPS62932 2.8 3.4 4
ILS_LIMITLow-side MOSFET current limitTPS62933 and TPS62933x2.93.84.5A
TPS62932 22.5

3

ILS_NOC Reverse current limit TPS62933F 1.2 2.4 3.6 A
IPEAK_MINMinimum peak inductor currentTPS62933, TPS62933P, and TPS62933O0.75A
TPS629320.53
SOFT START (SS PIN)
ISSSoft-start charge current TPS62932, TPS62933, and TPS62933F4.55.56.5μA
TSS Fixed internal soft-start time TPS62933P and TPS62933O 2 ms
POWER GOOD (PG PIN)
VPGTH PG threshold, VFB percentage VFB falling, PG high to low 85%
VFB rising, PG low to high 90%
VFB falling, PG low to high 110%
VFB rising, PG high to low 115%
TPG_R PG delay time PG from low to high 70 μs
TPG_F PG delay time PG from high to low 18 μs
VIN_PG_VALID Minimum VIN for valid PG output Measured when PG < 0.5 V with 100-kΩ pullup to external 5 V 2 2.5 V
VPG_OL PG output low-level voltage IPG = 0.5 mA 0.3 V
IPG_LK PG leakage current when open drain is high VPG = 5.5 V –1 1 μA
OSCILLATOR FREQUENCY (RT PIN)
fSWSwitching center frequencyRT = floating 450500550kHz
RT = GND 100012001350
RT = 71.5 kΩ 310
RT = 9.09 kΩ 2100
fSW_min Minimum switching frequency TPS62933O 30 kHz
tON_MIN(1)Minimum ON pulse width70ns
tOFF_MIN(1)Minimum OFF pulse width140ns
tON_MAX(1)Maximum ON pulse width7μs
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTION
VOVPOutput OVP thresholdOVP detect (L→H) 112%115%118%
Hysteresis 5%
VUVPOutput UVP thresholdUVP detect (H→L)65%
thiccup_ONUV hiccup ON time before entering hiccup mode after soft start ends256μs
thiccup_OFFUV hiccup OFF time before restart10.5 × tSSs
THERMAL SHUTDOWN
TSHDN(1)Thermal shutdown threshold Shutdown temperature165°C
THYS(1)Hysteresis30°C
SPREAD SPECTRUM FREQUENCY
fmModulation frequencyfSW / 128kHz
fspreadInternal spread oscillator frequency±6%
(1) Not production tested, specified by design.