SLVSD52A October   2015  – January 2016 TPS63020-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Application Schematic
  5. 5 Revision History
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Dynamic Voltage Positioning
      2. 9.3.2 Dynamic Current Limit
        1. 9.3.2.1 Device Enable
        2. 9.3.2.2 Power Good
        3. 9.3.2.3 Overvoltage Protection
        4. 9.3.2.4 Undervoltage Lockout
        5. 9.3.2.5 Overtemperature Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Softstart and Short Circuit Protection
      2. 9.4.2 Buck-Boost Operation
      3. 9.4.3 Control Loop
      4. 9.4.4 Power Save Mode and Synchronization
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Capacitor Selection
          1. 10.2.2.2.1 Input Capacitor
          2. 10.2.2.2.2 Output Capacitor
          3. 10.2.2.2.3 Bypass Capacitor
        3. 10.2.2.3 Setting the Output Voltage
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 2-A Load Current
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

DSJ Package
14-Pin VSON (QFN)
(Top View)
TPS63020-Q1 po_lvs916_ETP.gif
NOTE: *) The exposed thermal pad is connected to PGND.
See TPS63020-Q1 Pin FMEA Application Report SLVA736

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
EN 12 I Enable input (1 enabled, 0 disabled), must not be left open
FB 3 I Voltage feedback of adjustable versions.
GND 2 Control/logic ground
L1 8, 9 I Connection for inductor
L2 6, 7 I Connection for inductor
PG 14 O Output power good (1 good, 0 failure; open drain)
PGND Power ground
PS/SYNC 13 I Enable/disable power save mode (1 disabled, 0 enabled, clock signal for synchronization), must not be left open
VIN 10, 11 I Supply voltage for power stage
VINA 1 I Supply voltage for control stage
VOUT 4, 5 O Buck-boost converter output
Exposed Thermal Pad The exposed thermal pad is connected to PGND.