JAJSCD1B June   2016  – March 2019 TPS63070

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係、、Vo = 5V
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram TPS63070
    3. 8.3 Functional Block Diagram TPS630701
    4. 8.4 Feature Description
      1. 8.4.1  Control Loop Description
      2. 8.4.2  Precise Enable
      3. 8.4.3  Power Good
      4. 8.4.4  Soft Start
      5. 8.4.5  PS/SYNC
      6. 8.4.6  Short Circuit Protection
      7. 8.4.7  VSEL and FB2 pins
      8. 8.4.8  Overvoltage Protection
      9. 8.4.9  Undervoltage Lockout
      10. 8.4.10 Overtemperature Protection
    5. 8.5 Device Functional Modes
      1. 8.5.1 Power Save Mode
      2. 8.5.2 Current Limit
      3. 8.5.3 Output Discharge Function (TPS630702 only)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application for adjustable version
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming The Output Voltage
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Capacitor Selection
          1. 9.2.2.3.1 Input Capacitor
          2. 9.2.2.3.2 Output Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application for Fixed Voltage Version
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Thermal Information
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over VIN = 2V to 16V; Tj = -40°C to 125°C; typical values are at Tj = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input voltage range once started; Vout ≥ 3.0 V 2.0 16 V
VIN Input voltage range for start-up; Vout < 3.0 V 3.0 16 V
IOUT Output current during operation with either
VIN ≥ 4.5 V or VOUT ≥ 4.5 V
and the boost factor
(VOUT/VIN) ≤ 1		 2 A
IQ Quiescent current into VIN; IOUT= 0 mA,
VEN = VIN = 6 V, PFM
VOUT = 5 V; Tj = -40°C to 85°C		 54 103 μA
IQ Quiescent current into VIN; IOUT= 0 mA,
VEN = VIN = 6 V, PFM
VOUT = 5 V; Tj = -40°C to 125°C		 133 μA
IQ Quiescent current into VOUT; IOUT= 0 mA,
VEN = VIN = 6 V, VOUT = 5 V, PFM
Tj = -40°C to 85°C		 5 9 μA
IQ Quiescent current into VOUT; IOUT= 0 mA,
VEN = VIN = 6 V, VOUT = 5 V, PFM
Tj = -40°C to 125°C		 17 μA
ISD Shutdown current VEN = 0 V; Tj = -40°C to 85°C;
VIN = 5V		 2 12 μA
ISD Shutdown current VEN = 0 V; Tj = -40°C to 85°C 26 μA
VUVLO Undervoltage lockout threshold VIN voltage falling 1.7 1.85 1.95 V
VUVLO,TH Undervoltage lockout hysteresis VIN voltage rising 525 850 mV
TSD Thermal shutdown 160 °C
TSD Thermal shutdown hysteresis 20 °C
LOGIC SIGNALS: EN, PS/SYNC, PG, VSEL
VTHR Threshold Voltage rising edge for EN pin and PS/SYNC used for PWM/PFM mode change 0.77 0.8 0.83 V
VTHF Threshold Voltage falling edge for EN pin and PS/SYNC used for PWM/PFM mode change 0.67 0.7 0.73 V
VIL VSEL low level input voltage; PS/SYNC low level input voltage when used for synchronization 0.3 V
VIH VSEL high level input voltage; PS/SYNC high level input voltage when used for synchronization 1.1 V
EN, PS/SYNC, VSEL input current 0.2 μA
VOL PG output low voltage IPG = -1 mA 0.4 V
ILKG PG output leakage current PG pin high impedance; VPG = 5 V 0.2 μA
IPG PG sink current 1 mA
VTH_PG Power Good Threshold Voltage, rising Vout 94.5 96 98.5 %
VTH_PG Power Good Threshold Voltage, falling Vout 90 92 94.5 %
OUTPUT
VOUT TPS63070/TPS630702 output voltage range(1) 2.5 9 V
VOUT TPS630701 output voltage 5.0 V
VFB TPS63070/TPS630702 feedback voltage PS/SYNC = VIN 800 mV
feedback impedance for fixed voltage versions 1.5 MΩ
feedback leakage for adjustable version; VFB = 0.8V 100 nA
VFB TPS63070/TPS630702 feedback voltage accuracy PS/SYNC = GND (PWM mode) -1 1 %
VOUT TPS630701 output voltage accuracy PS/SYNC = GND (PWM mode) -1 1 %
VFB TPS63070/TPS630702 feedback voltage accuracy PS/SYNC = VIN (PFM mode);
VIN ≥ 3V		 -1 3 %
VOUT TPS630701 output voltage accuracy PS/SYNC = VIN (PFM mode);
VIN ≥ 3V		 -1 3 %
fSW Oscillator frequency 2100 2400 2700 kHz
Frequency range for synchronization 2100 2800 kHz
IIN,max Average, positive input current limit VIN = 5.0V; VOUT = 6.5V;
Tj = 0°C to 125°C		 3050 3600 4150 mA
IIN,max Average, negative input current limit VIN = 5.0V; VOUT = 6.5V;
Tj = 0°C to 125°C		 1100 1800 mA
RDS(ON)-BUCK High side switch on resistance VIN = 5 V 50 80 mΩ
Low side switch on resistance VIN = 5 V 100 160 mΩ
RDS(ON)-BOOST High side switch on resistance VIN = 5 V 40 70 mΩ
Low side switch on resistance VIN = 5 V 80 125 mΩ
RDS(ON)-FB2 FB2 resistance to GND
with VSEL = high		 25 100 Ω
ILKG Input leakage current into FB2
with VSEL=low		 VFB = VFB2 = 0.8V 100 nA
FB2 sink current 100 μA
Line regulation Power Save Mode disabled 0.07 %/V
Load regulation Power Save Mode disabled 0.2 %/A
VAUX Maximum bias voltage VIN ≥ VOUT; VIN < 6V VIN - 0.3 7 V
VIN < VOUT VOUT - 0.3 7 V
ROD Output discharge resistance (only in TPS630702) VIN = 5 V; VOUT = 5V 200 Ω
tdelay Start-up delay time from EN = VIH to device starts switching 70 μs
tSS soft-start time time to ramp from 5% to 95% of Vout; buck mode; VIN = 7.2 V,
Vout = 3.3 V, Iout = 500 mA		 400 μs
time to ramp from 5% to 95% of Vout; boost mode; VIN = 3.0 V,
Vout = 3.3 V, Iout = 250 mA		 850 μs
(1) Please observe the minimum duty cycle in buck mode