JAJSCD1B June   2016  – March 2019 TPS63070

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係、、Vo = 5V
  4. 改訂履歴
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram TPS63070
    3. 8.3 Functional Block Diagram TPS630701
    4. 8.4 Feature Description
      1. 8.4.1  Control Loop Description
      2. 8.4.2  Precise Enable
      3. 8.4.3  Power Good
      4. 8.4.4  Soft Start
      5. 8.4.5  PS/SYNC
      6. 8.4.6  Short Circuit Protection
      7. 8.4.7  VSEL and FB2 pins
      8. 8.4.8  Overvoltage Protection
      9. 8.4.9  Undervoltage Lockout
      10. 8.4.10 Overtemperature Protection
    5. 8.5 Device Functional Modes
      1. 8.5.1 Power Save Mode
      2. 8.5.2 Current Limit
      3. 8.5.3 Output Discharge Function (TPS630702 only)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application for adjustable version
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming The Output Voltage
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Capacitor Selection
          1. 9.2.2.3.1 Input Capacitor
          2. 9.2.2.3.2 Output Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application for Fixed Voltage Version
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Thermal Information
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout Guidelines

For all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground connection. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise. Connect these ground nodes at any place close to one of the ground pin of the IC.

A ceramic capacitor each, as close as possible from the VIN pin to GND and one from the VOUT pin to GND, shown as C1 and C4 in the layout proposal are used to suppress high frequency noise. The case size should be 0603 or smaller for good high frequency performance. Additional 0805 size input and output capacitors are used to get the required capacitance on the input and output depending on the supply voltage range and the output voltage.

The feedback divider should be placed as close as possible to the feedback pin of the IC. To lay out the control ground, short traces are recommended as well, separation from the power ground traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and control ground current.

In case any of the digital inputs EN, VSEL or PS/SYNC need to be tied to the input supply voltage VIN, a 10k resistor must be used in series. One common resistor for all digital inputs that are tied to VIN is sufficient.