JAJSDT9A September   2017  – July 2018 TPS63710

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      標準アプリケーション
      2.      VOUT = -1.8V時の効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1. Table 1. Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low Noise Reference System
      2. 7.3.2 Duty Cycle
      3. 7.3.3 Enable
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Thermal Shutdown
      6. 7.3.6 Power Good Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Soft-Start
      2. 7.4.2 VOUT Discharge
      3. 7.4.3 Current Limit
      4. 7.4.4 CCP Capacitor Precharge
      5. 7.4.5 PWM Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting the Output Voltage
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Capacitor Selection
          1. 8.2.2.4.1 CCP Capacitor
          2. 8.2.2.4.2 Input Capacitor
          3. 8.2.2.4.3 Output Capacitor
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Parameter Measurement Information
    3. 8.3 System Examples
      1. 8.3.1 Typical Application for Powering the Negative Rail of a Gallium Nitride (GaN) Power Amplifier
      2. 8.3.2 Typical Application for Powering the Negative Rail of an ADC or DAC
      3. 8.3.3 Typical Application for Laser Diode Bias
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 WEBENCH®ツールによるカスタム設計
      2. 11.1.2 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.2 Setting the Output Voltage

The output voltage of the TPS63710 converter is adjusted with an external resistor divider connected to the FB pin. The voltage at the feedback pin is negative and is regulated to -0.7 V. The gain stage adds a gain factor of 1/0.9 such that the output voltage is -0.778 V for -0.7 V of FB voltage. See Low Noise Reference System for details.

The value of the output voltage is set by the selection of the resistive divider using Equation 3 and VFB_SET = -0.778 V. Both VOUT and VFB_SET are negative, so the ratio is positive again.

Equation 3. TPS63710 equation_VFB.gif

It is recommended to choose resistor values such that R1 + R2 are in a range from 100 kΩ to 500 kΩ. For example, if an output voltage of -1.8 V is needed and a resistor of 150-kΩ has been chosen for R2, a 196-kΩ resistor on R1 is required to program the desired output voltage.

Table 4. Recommended Resistor Values

Output Voltage R1 R2
-1 V 51.1 kΩ 180 kΩ
-1.8 V 196 kΩ 150 kΩ
-2.5 V 287 kΩ 130 kΩ
-5 V 130 kΩ 24 kΩ

For proper regulation, the minimum input voltage should remain at least above the output voltage, per Equation 4:

Equation 4. TPS63710 equation_minVIN.gif

See Figure 36 to Figure 38 for the recommended input voltage levels to generate a specific output voltage.