JAJSDT9A September   2017  – July 2018 TPS63710

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      標準アプリケーション
      2.      VOUT = -1.8V時の効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1. Table 1. Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low Noise Reference System
      2. 7.3.2 Duty Cycle
      3. 7.3.3 Enable
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Thermal Shutdown
      6. 7.3.6 Power Good Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Soft-Start
      2. 7.4.2 VOUT Discharge
      3. 7.4.3 Current Limit
      4. 7.4.4 CCP Capacitor Precharge
      5. 7.4.5 PWM Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting the Output Voltage
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Capacitor Selection
          1. 8.2.2.4.1 CCP Capacitor
          2. 8.2.2.4.2 Input Capacitor
          3. 8.2.2.4.3 Output Capacitor
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Parameter Measurement Information
    3. 8.3 System Examples
      1. 8.3.1 Typical Application for Powering the Negative Rail of a Gallium Nitride (GaN) Power Amplifier
      2. 8.3.2 Typical Application for Powering the Negative Rail of an ADC or DAC
      3. 8.3.3 Typical Application for Laser Diode Bias
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 WEBENCH®ツールによるカスタム設計
      2. 11.1.2 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.1 Layout Guidelines

For all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current paths, and for the power-ground tracks. The input, output and CP capacitors should be placed as close as possible to the IC. Because CVAUX carries the peak currents of the gate control block, it should have a compact and direct routing to the VAUX and GND pin 10, staying away from sensitive signals. The CAP, FB, and VREF pins should all be routed close to the IC in order to keep them away from external noise. The total resistance of the voltage divider R1 + R2 must be kept in the range as defined in the Recommended Operating Conditions.

The pinout of the device has been defined such that the external components can be placed directly at the pins to allow for a simplified external layout and good performance. Thermal and electrical vias should be used under the exposed thermal pad to the GND plane.