The TPS65011 device is an integrated power and battery management IC for applications powered by one Li-Ion or Li-Polymer cell and which require multiple power rails. The TPS65011 provides two highly efficient, 1.25-MHz step-down converters targeted at providing the core voltage and peripheral, I/O rails in a processor-based system. Both step-down converters enter a low-power mode at light load for maximum efficiency across the widest possible range of load currents.
The TPS65011 also integrates two 200-mA LDO voltage regulators, which are enabled via the serial interface. Each LDO operates with an input voltage range between 1.8 V and 6.5 V, allowing them to be supplied from one of the step-down converters or directly from the battery.
The TPS65011 also has a highly integrated and flexible Li-Ion linear charger and system power management. It offers integrated USB-port and AC-adapter supply management with autonomous power-source selection, power FET and current sensor, high accuracy current and voltage regulation, charge status, and charge termination.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS65011 | VQFN (48) | 7.00 mm × 7.00 mm |
Changes from A Revision (January 2005) to B Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CHARGER SECTION | |||
AC | 40 | I | Charger input voltage from AC adapter. The AC pin can be left open or can be connected to ground if the charger is not used. |
AGND2 | 44 | — | Analog ground connection. All analog ground pins are connected internally on the chip. |
ISET | 37 | I | External charge current setting resistor connection for use with AC adapter |
PG | 11 | O | Indicates when a valid power supply is present for the charger (open drain) |
Thermal Pad | - | — | Connect the thermal pad to GND |
TS | 38 | I | Battery temperature sense input |
USB | 43 | I | Charger input voltage from USB port. The USB pin can be left open or can be connected to ground if the charger is not used. |
VBAT_A | 41 | I | Sense input for the battery voltage. Connect directly with the battery. |
VBAT_B | 42 | O | Power output of the battery charger. Connect directly with the battery. |
SWITCHING REGULATOR SECTION | |||
AGND3 | 45 | — | Analog ground connection. All analog ground pins are connected internally on the chip. |
L1_A | 9 | — | Switch pin of VMAIN converter. The VMAIN inductor is connected here. |
L1_B | 10 | ||
L2 | 4 | — | Switch pin of VCORE converter. The VCORE inductor is connected here. |
PGND1_A | 15 | — | Power ground for VMAIN converter |
PGND1_B | 16 | ||
PGND2 | 46 | — | Power ground for VCORE converter |
VCC | 6 | I | Power supply for digital and analog circuitry of MAIN and CORE DC-DC converters. This must be connected to the same voltage supply as VINCORE and VINMAIN. Also supplies serial interface block |
VCORE | 48 | I | VCORE feedback voltage sense input, connect directly to VCORE |
VINCORE | 5 | I | Input voltage for VCORE step-down converter. This must be connected to the same voltage supply as VINMAIN and VCC. |
VINMAIN_A | 7 | I | Input voltage for VMAIN step-down converter. This must be connected to the same voltage supply as VINCORE and VCC. |
VINMAIN_B | 8 | ||
VMAIN | 13 | I | VMAIN feedback voltage sense input, connect directly to VMAIN |
LDO REGULATOR SECTION | |||
AGND1 | 21 | — | Analog ground connection. All analog ground pins are connected internally on the chip. |
VFB_LDO1 | 23 | I | Feedback input from external resistive divider for LDO1 |
VINLDO1 | 22 | I | Input voltage for LDO1 |
VINLDO2 | 19 | I | Input voltage for LDO2 |
VLDO1 | 24 | O | Output voltage for LDO1 |
VLDO2 | 20 | O | Output and feedback voltage for LDO2 |
DRIVER SECTION | |||
LED2 | 2 | O | LED driver, with blink rate programmable via serial interface |
VIB | 3 | O | Vibrator driver, enabled via serial interface |
CONTROL AND I2C SECTION | |||
BATT_COVER | 39 | I | Indicates if battery cover is in place |
DEFCORE | 1 | I | Input signal indicating default VCORE voltage, 0 = 1.3 V, 1 = 1.6 V |
DEFMAIN | 12 | I | Input signal indicating default VMAIN voltage, 0 = 1.8 V, 1 = 3.3 V |
GPIO1 | 26 | I/O | General-purpose open-drain input/output |
GPIO2 | 25 | I/O | General-purpose open-drain input/output |
GPIO3 | 18 | I/O | General-purpose open-drain input/output |
GPIO4 | 17 | I/O | General-purpose open-drain input/output |
HOT_RESET | 31 | I | Push-button reset input used to reboot or wakeup processor via TPS65013 |
IFLSB | 28 | I | LSB of serial interface address used to distinguish two devices with the same address |
INT | 35 | O | Indicates a charge fault or termination, or if any of the regulator outputs are below the lower tolerance level, active low (open drain) |
LOW_PWR | 36 | I | Input signal indicating deep-sleep mode, VCORE is lowered to predefined value or disabled |
MPU_RESET | 32 | O | Open-drain reset output generated by user activated HOT_RESET |
PB_ONOFF | 47 | I | Push-button enable pin, also used to wakeup processor from low-power mode |
PS_SEQ | 14 | I | Sets power-up/down sequence of step-down converters |
PWRFAIL | 34 | O | Open-drain output. Active low when UVLO comparator indicates low VBAT condition or when shutdown is about to occur due to an overtemperature condition or when the battery cover is removed (BATT_COVER has gone low). |
RESPWRON | 33 | O | Open-drain system reset output, generated according to the state of the VMAIN output voltage. If the main output is disabled, RESPWRON is active (i.e., low). |
SCLK | 30 | I | Serial interface clock line |
SDAT | 29 | I/O | Serial interface data/address |
TPOR | 27 | I | Sets the reset delay time at RESPWRON. TPOR = 0: Tn(RESPWRON) = 100 ms. TPOR = 1: Tn(RESPWRON) = 1 s. |