SLVS504B March   2004  – September  2015 TPS65012

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Battery Charger Electrical Characteristics
    7. 6.7 Serial Interface Timing Requirements
    8. 6.8 Dissipation Ratings
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Battery Charger
        1. 7.3.1.1 Autonomous Power Source Selection
        2. 7.3.1.2 Temperature Qualification
        3. 7.3.1.3 Battery Preconditioning
        4. 7.3.1.4 Battery Charge Current
        5. 7.3.1.5 Battery Voltage Regulation
        6. 7.3.1.6 Charge Termination and Recharge
        7. 7.3.1.7 Sleep Mode
        8. 7.3.1.8 PG Output
        9. 7.3.1.9 Thermal Considerations for Setting Charge Current
      2. 7.3.2 Step-Down Converters, VMAIN and VCORE
        1. 7.3.2.1 Power-Save Mode Operation
        2. 7.3.2.2 Forced PWM
        3. 7.3.2.3 Dynamic Voltage Positioning
        4. 7.3.2.4 Soft Start
        5. 7.3.2.5 100% Duty Cycle Low-Dropout Operation
        6. 7.3.2.6 Active Discharge When Disabled
        7. 7.3.2.7 Power-Good Monitoring
        8. 7.3.2.8 Overtemperature Shutdown
      3. 7.3.3 Low-Dropout Voltage Regulators
        1. 7.3.3.1 Power-Good Monitoring
        2. 7.3.3.2 Enable and Sequencing
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Power-Up Sequencing
      6. 7.3.6 System Reset and Control Signals
      7. 7.3.7 Vibrator Driver
    4. 7.4 Device Functional Modes
      1. 7.4.1 TPS65012 Power States Description
        1. 7.4.1.1 State 1: No Power
        2. 7.4.1.2 State 2: ON
        3. 7.4.1.3 State 3: Low-Power Mode
        4. 7.4.1.4 State 4: Shutdown
    5. 7.5 Programming
      1. 7.5.1 LED2 Output
      2. 7.5.2 Interrupt Management
      3. 7.5.3 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1  CHGSTATUS Register (Address: 01h—Reset: 00h)
      2. 7.6.2  REGSTATUS Register (Address: 02h—Reset: 00h)
      3. 7.6.3  MASK1 Register (Address: 03h—Reset: FFh)
      4. 7.6.4  MASK2 Register (Address: 04h—Reset: FFh)
      5. 7.6.5  ACKINT1 Register (Address: 05h—Reset: 00h)
      6. 7.6.6  ACKINT2 Register (Address: 06h—Reset: 00h)
      7. 7.6.7  CHGCONFIG Register Address: 07h—Reset: 1Bh
      8. 7.6.8  LED1_ON Register (Address: 08h—Reset: 00h)
      9. 7.6.9  LED1_PER Register (Address: 09h—Reset: 00h)
      10. 7.6.10 LED2_ON Register (Address: 0Ah—Reset: 00h)
      11. 7.6.11 LED2_PER (Register Address: 0Bh—Reset: 00h)
      12. 7.6.12 VDCDC1 Register (Address: 0Ch—Reset: 72h/73h)
      13. 7.6.13 VDCDC2 Register (Address: 0Dh—Reset: 68h/78h)
      14. 7.6.14 VREGS1Register (Address: 0Eh—Reset: 88h)
      15. 7.6.15 MASK3 Register (Address: 0Fh—Reset: 00h)
      16. 7.6.16 DEFGPIO Register Address: (10h—Reset: 00h)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS65012 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Inductor Selection for the Main and the Core Converter
          2. 8.2.1.2.2 Output Capacitor Selection
          3. 8.2.1.2.3 Input Capacitor Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Low-Power Mode
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. Power Supply Recommendations
    1. 9.1 LDO1 Output Voltage Adjustment
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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7 Detailed Description

7.1 Overview

The TPS65012 charger automatically selects the USB port or the AC adapter as the power source for the system. In the USB configuration, the host can increase the charge current from the default value of maximum 100 mA to 500 mA via the interface. In the AC-adapter configuration, an external resistor sets the maximum value of charge current.

The battery is charged in three phases: conditioning, constant current, and constant voltage. Charge is normally terminated based on minimum current. An internal charge timer provides a safety backup for charge termination. The TPS65012 device automatically restarts the charge if the battery voltage falls below an internal threshold. The charger automatically enters sleep mode when both supplies are removed.

The serial interface can be used for dynamic voltage scaling, for collecting information on and controlling the battery charger status, for optionally controlling 2 LED driver outputs, a vibrator driver, masking interrupts, or for disabling/enabling and setting the LDO output voltages. The interface is compatible with the fast/standard mode specification allowing transfers at up to 400 kHz.

Battery Charger, Step-Down Converters, LDOs, UVLO protection, Rail Sequencing, Vibrator Driver, and various logic level controls. The LOW_PWR pin allows the core converter to lower its output voltage when the application processor goes into deep sleep.

7.2 Functional Block Diagram

TPS65012 fbd_lvs504.gif

7.3 Feature Description

7.3.1 Battery Charger

The TPS65012 supports a precision Li-Ion or Li-Polymer charging system suitable for single cells with either coke or graphite anodes. Charging the battery is possible even without the application processor being powered up. The TPS65012 starts charging when an input voltage on either AC or USB input is present, which is greater than the charger UVLO threshold. See Figure 26 for a typical charge profile.

TPS65012 ai_charge_lvs149.gif Figure 26. Typical Charging Profile

7.3.1.1 Autonomous Power Source Selection

Per default the TPS65012 attempts to charge from the AC input. If AC input is not present, the USB is selected. If both inputs are available, the AC input has priority. The charge current is initially limited to 100 mA when charging from the USB input. This can be increased to 500 mA via the serial interface. The charger can be completely disabled via the interface, and it is also possible just to disable charging from the USB port. The start of the charging process from the USB port is delayed in order to allow the application processor time to disable USB charging, for example, if a USB OTG port is recognized. The recommended input voltage for charging from the AC input is 4.5 V < VAC < 5.5 V. However, the TPS65012 is capable of withstanding (but not charging from) up to 20 V. Charging is disabled if VAC is greater than typically 6.6 V.

7.3.1.2 Temperature Qualification

The TPS65012 continuously monitors battery temperature by measuring the voltage between the TS and AGND pins. An internal current source provides the bias for most common 10K negative-temperature coefficient thermistors (NTC) (see Figure 27). The IC compares the voltage on the TS pin against the internal V(LTF) and V(HTF) thresholds to determine if charging is allowed. Once a temperature outside the V(LTF) and V(HTF) thresholds is detected, the IC immediately suspends the charge. The IC suspends charge by turning off the power FET and holding the timer value (i.e., timers are not reset). Charge is resumed when the temperature returns to the normal range.

The allowed temperature range for 103-A T-type thermistor is 0°C to 45°C. However, the user may modify these thresholds by adding two external resistors. See Figure 28.

TPS65012 ai_TSpin_Con_lvs149.gif Figure 27. TS Pin Configuration
TPS65012 ai_TSpin_thr_lvs149.gif Figure 28. TS Pin Threshold

7.3.1.3 Battery Preconditioning

On power up, if the battery voltage is below the V(LOWV) threshold, the TPS65012 applies a precharge current, I(PRECHG), to the battery. This feature revives deeply discharged cells. The charge current during this phase is one tenth of the value in current regulation phase which is set with IO(out) = KSET × V(SET)/R(SET). The load current in preconditioning phase must be lower than I(PRECHG) and must allow the battery voltage to rise above V(LOWV) within t(Prechg). VBAT_A is the sense pin to the voltage comparator for the battery voltage. This allows a power-on sense measurement if the VBAT_A and VBAT_B pins are connected together at the battery.

The TPS65012 activates a safety timer, t(PRECHG), during the conditioning phase. If V(LOWV) threshold is not reached within the timer period, the TPS65012 turns off the charger and indicates the fault condition in the CHGSTATUS register. In the case of a fault condition, the TPS65012 reduces the current to I(DETECT). I(DETECT)is used to detect a battery replacement condition. Fault condition is cleared by power-on-reset (POR) or battery replacement or via the serial interface.

7.3.1.4 Battery Charge Current

TPS65012 offers on-chip current regulation. When charging from an AC adapter, a resistor connected between the ISET1 and AGND pins determines the charge rate. A maximum of 1-A charger current from the AC adapter is allowed. When charging from a USB port either a 100-mA or 500-mA charge rate can be selected via the serial interface; default is 100 mA maximum. Two bits are available in the CHGCONFIG register in the serial interface to reduce the charge current in 25% steps. These only influence charging from the AC input and may be of use if charging is often suspended due to excessive junction temperature in the TPS65012 (e.g., at high AC input voltages) and low battery voltages.

7.3.1.5 Battery Voltage Regulation

The voltage regulation feedback is through the VBAT pin. This pin is tied directly to the positive side of the battery pack. The TPS65012 monitors the battery-pack voltage between the VBAT and AGND pins. The TPS65012 is offered in a fixed-voltage version of 4.2 V.

As a safety backup, the TPS65012 also monitors the charge time in the fast-charge mode. If taper current is not detected within this time period, t(CHG), the TPS65012 turns off the charger and indicates FAULT in the CHGSTATUS register. In the case of a FAULT condition, the TPS65012 reduces the current to I(DETECT). I(DETECT) is used to detect a battery replacement condition. Fault condition is cleared by POR via the serial interface. Note that the safety timer is reset if the TPS65012 is forced out of the voltage regulation mode. The fast-charge timer is disabled by default to allow charging during normal operation of the end equipment. It is enabled via the CHGCONFIG register.

7.3.1.6 Charge Termination and Recharge

The TPS65012 monitors the charging current during the voltage regulation phase. Once the taper threshold, I(TAPER), is detected, the TPS65012 initiates the taper timer, t(TAPER). Charge is terminated after the timer expires. The TPS65012 resets the taper timer in the event that the charge current returns above the taper threshold, I(TAPER). After a charge termination, the TPS65012 restarts the charge once the voltage on the VBAT pin falls below the V(RCH) threshold. This feature keeps the battery at full capacity at all times. The fast charge timer and the taper timer must be enabled by programming CHGCONFIG(5)=1. A thermal suspend will suspend the fast-charge and taper timers.

In addition to the taper current detection, the TPS65012 terminates charge in the event that the charge current falls below the I(TERM) threshold. This feature allows for quick recognition of a battery removal condition. When a full battery is replaced with an empty battery, the TPS65012 detects that the VBAT voltage is below the recharge threshold and starts charging the new battery. The taper and termination bits are cleared in the CHGSTATUS register and if the INT pin is still active due to these two interrupt sources, then it is de-asserted. Depending on the transient seen at the VCC pin, all registers may be set to their default values and require reprogramming with any nondefault values required, such as enabling the fast-charge timer and taper termination; this should only happen if VCC drops below approximately 2 V.

7.3.1.7 Sleep Mode

The TPS65012 charger enters the low-power sleep mode if both input sources are removed from the circuit. This feature prevents draining the battery during the absence of input power.

7.3.1.8 PG Output

The open-drain power-good (PG) output indicates when a valid power supply is present for the charger. This can be either from the AC adapter input or from the USB. The output turns ON when a valid voltage is detected. A valid voltage is detected whenever the voltage on either pin AC or pin USB rises above the voltage on VBAT plus 100 mV. This output is turned off in the sleep mode. The PG pin can be used to drive an LED or communicate to the host processor. A voltage greater than the V(CHGOVLO) threshold (typ 6.6 V) at the AC input is not valid and does not activate the PG output. The PG output is held in high impedance state if the charger is in reset by programming CHGCONFIG(6)=1.

The PG output can also be programmed via the LED1_ON and LED1_PER registers in the serial interface. It can then be programmed to be permanently on, off, or to blink with defined on- and period-times. PG is controlled per default via the charger.

7.3.1.9 Thermal Considerations for Setting Charge Current

The TPS65012 is housed in a 48-pin QFN package with exposed leadframe on the underside. This 7 mm × 7 mm package exhibits a thermal impedance (junction-to-ambient) of 33 K/W when mounted on a JEDEC high-K board with zero air flow.

Table 2. Thermal Considerations for Setting Charge Current

AMBIENT TEMPERATURE MAX POWER DISSIPATION FOR Tj= 125°C DERATING FACTOR ABOVE TA= 55°C
25°C 3 W 30 mW/°C
55°C 2.1 W

Consideration needs to be given to the maximum charge current when the assembled application board exhibits a thermal impedance, which differs significantly from the JEDEC high-K board. The charger has a thermal shutdown feature, which suspends charging if the TPS65012 junction temperature rises above a threshold of 145°C. This threshold is set 15°C below the threshold used to power down the TPS65012 completely.

7.3.2 Step-Down Converters, VMAIN and VCORE

The TPS65012 incorporates two synchronous step-down converters operating typically at 1.25 MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the converters automatically enter power-save mode and operate with pulse frequency modulation (PFM). The main converter is capable of delivering 1-A output current, and the core converter is capable of delivering 400 mA.

The converter output voltages are programmed via the VDCDC1 and VDCDC2 registers in the serial interface. The main converter defaults to 3-V or 3.3-V output voltage depending on the DEFMAIN configuration pin, if DEFMAIN is tied to ground, the default is 3 V; if it is tied to VCC the default is 3.3 V. The core converter defaults to either 1.5 V or 1.6 V depending on whether the DEFCORE configuration pin is tied to GND or to VCC, respectively. Both the main and core output voltages can subsequently be reprogrammed after start-up via the serial interface. In addition, the LOW_PWR pin can be used either to lower the core voltage to a value defined in the VDCDC2 register when the application processor is in deep sleep mode or to disable the core converter. An active signal at LOW_PWR is ignored if the ENABLE_LP bit is not set in the VDCDC1 register.

The step-down converter outputs (when enabled) are monitored by power-good comparators, the outputs of which are available via the serial interface. The outputs of the DC-DC converters can be optionally discharged when the DC-DC converters are disabled.

During PWM operation, the converters use a unique fast-response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch in case the current limit of the P-channel switch is exceeded. After the dead time preventing current shoot through, the N-channel MOSFET rectifier is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel rectifier and turning on the P-channel switch.

The error amplifier, together with the input voltage, determines the rise time of the saw-tooth generator, and therefore, any change in input voltage or output voltage directly controls the duty cycle of the converter giving a good line and load transient regulation.

The two DC-DC converters operate synchronized to each other, with the MAIN converter as the master. A 270° phase shift between the MAIN switch turn on and the CORE switch turn on decreases the input RMS current, and smaller input capacitors can be used. This is optimized for a typical application where the MAIN converter regulates a Li-Ion battery voltage of 3.7 V to 3.3 V and the CORE from 3.7 V to 1.5 V.

7.3.2.1 Power-Save Mode Operation

As the load current decreases, the converter enters the power-save mode operation. During power save mode, the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency.

In order to optimize the converter efficiency at light load, the average current is monitored; if in PWM mode, the inductor current remains below a certain threshold, then power-save mode is entered. The typical threshold can be calculated as:

Equation 1. TPS65012 Q_Iskip_lvs149.gif

During the power-save mode, the output voltage is monitored with the comparator by the thresholds comp low and comp high. As the output voltage falls below the comp-low threshold, set to typically 0.8% above the nominal Vout, the P-channel switch turns on. The converter then runs at 50% of the nominal switching frequency. If the load is below the delivered current, then the output voltage rises until the comp-high threshold is reached, typically 1.6% above the nominal Vout. At this point, all switching activity ceases, hence reducing the quiescent current to a minimum until the output voltage has dropped below comp low again. If the load current is greater than the delivered current, then the output voltage falls until it crosses the nominal output voltage threshold (comp-low 2 threshold), whereupon power-save mode is exited, and the converter returns to PWM mode.

These control methods reduce the quiescent current typically to 12-µA per converter and the switching frequency to a minimum achieving the highest converter efficiency. Setting the comparator thresholds to typically 0.8% and 1.6% above the nominal output voltage at light load current results in a dynamic voltage positioning achieving lower absolute voltage drops during heavy load transient changes. This allows the converters to operate with a small output capacitor of just 10 µF for the core and 22 µF for the main output and still have a low absolute voltage drop during heavy load transient changes. See Figure 29 for detailed operation of the power-save mode. The power-save mode can be disabled through the I2C interface to force the converters to stay in fixed frequency PWM mode.

TPS65012 ai_PSM_thre_lvs149.gif Figure 29. Power-Save Mode Thresholds and Dynamic Voltage Positioning

7.3.2.2 Forced PWM

The core and main converters are forced into PWM mode by setting bit 7 in the VDCDC1 register. This feature minimizes ripple on the output voltages.

7.3.2.3 Dynamic Voltage Positioning

As described in the power-save mode operation sections and as detailed in Figure 13, the output voltage is typically 1.2% above the nominal output voltage at light load currents as the device is in power-save mode. This gives additional headroom for the voltage drop during a load transient from light load to full load. During a load transient from full load to light load, the voltage overshoot is also minimized due to active regulation turning on the N-channel rectifier switch.

7.3.2.4 Soft Start

Both converters have an internal soft start circuit that limits the inrush current during start-up. The soft start is implemented as a digital circuit increasing the switch current in 4 steps up to the typical maximum switch current limit of 700 mA (core) and 1.75 A (main). Therefore, the start-up time mainly depends on the output capacitor and load current.

7.3.2.5 100% Duty Cycle Low-Dropout Operation

The TPS65012 converters offer a low input to output voltage difference while maintaining operation with the use of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage and is calculated as:

Equation 2. TPS65012 Q_VI_min_lvs149.gif

where

  • IO(max) = maximum output current plus inductor ripple current
  • rDS(on)max= maximum P-channel switch rDS(on).
  • RL = DC resistance of the inductor
  • VO(max)= nominal output voltage plus maximum output voltage tolerance

7.3.2.6 Active Discharge When Disabled

When the CORE and MAIN converters are disabled, due to an UVLO, BATT_COVER or OVERTEMP condition, it is possible to actively pull down the outputs. This feature is disabled per default and is individually enabled via the VDCDC1 and VDCDC2 registers in the serial interface. When this feature is enabled, the core and main outputs are discharged by a 400-Ω (typical) load.

7.3.2.7 Power-Good Monitoring

Both the MAIN and CORE converters have power-good comparators. Each comparator indicates when the relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these comparators are available in the REGSTATUS register via the serial interface. A maskable interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when the converters are disabled.

7.3.2.8 Overtemperature Shutdown

The MAIN and CORE converters are automatically shut down if the temperature exceeds the trip point (see the electrical characteristics). This detection is only active if the converters are in PWM mode, either by setting FPWM = 1, or if the output current is high enough that the device runs in PWM mode automatically.

7.3.3 Low-Dropout Voltage Regulators

The low-dropout voltage regulators are designed to operate with low value ceramic input and output capacitors. They operate with input voltages down to 1.8 V. The LDOs offer a maximum dropout voltage of 300 mV at rated output current. Each LDO has a current limit feature. Both LDOs are enabled per default; both LDOs can be disabled or programmed via the serial interface using the VREGS1 register. The LDO outputs (when enabled) are monitored by power-good comparators, the outputs of which are available via the serial interface. The LDOs also have reverse conduction prevention when disabled. This allows the possibility to connect external regulators in parallel in systems with a backup battery.

7.3.3.1 Power-Good Monitoring

Both the LDO1 and LDO2 linear regulators have power-good comparators. Each comparator indicates when the relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these comparators are available in the REGSTATUS register via the serial interface. An interrupt is generated when any voltage rail drops below the 10% threshold. The LDO2 comparator is disabled when LDO2 is disabled. The LDO1 power good comparator is always active since it generates the system reset signal, RESPWRON, see the System Reset and Control Signal Section below. This also allows the possibility to monitor VLDO1, even if it is provided by an external regulator.

7.3.3.2 Enable and Sequencing

Enabling and sequencing of the DC-DC converters and LDOs are described in the power-up sequencing section. The OMAP1510 processor from Texas Instruments requires that the core power supply is enabled before the I/O power supply, which means that the CORE converter should power up before the MAIN converter. This is achieved by connecting PS_SEQ to GND.

7.3.4 Undervoltage Lockout

The undervoltage lockout circuit for the four regulators on TPS65012 prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery. Basically, it prevents the converter from turning on the power switch or rectifier FET under undefined conditions. The undervoltage threshold voltage is set by default to 3.25 V. After power up, the threshold voltage can be reprogrammed through the serial interface. The undervoltage lockout comparator compares the voltage on the VCC pin with the UVLO threshold. When the VCC voltage drops below this threshold, the TPS65012 sets the PWRFAIL pin low and after a time t(UVLO) disables the voltage regulators in the sequence defined by PS_SEQ. The same procedure is followed when the TPS65012 detects that its junction temperature has exceeded the overtemperature threshold, typically 160°C, with a delay t(overtemp). The TPS65012 automatically restarts when the UVLO (or overtemperature) condition is no longer present.

The battery charger circuit has a separate UVLO circuit with a threshold of typically 2.5 V, which is compared with the voltage on AC and USB supply pins.

7.3.5 Power-Up Sequencing

The TPS65012 power-up sequencing allows the maximum flexibility without generating excessive logistical or system complexity. The relevant control pins are described in the following table:

Table 3. Control Pins

PIN NAME INPUT OR OUTPUT FUNCTION
PS_SEQ I Input signal indicating power-up and -down sequence of the switching converters. PS_SEQ = 0 forces the core regulator to ramp up first and down last. PS_SEQ = 1 forces the main regulator to ramp up first and down last.
DEFCORE I Defines the default voltage of the VCORE switching converter. DEFCORE = 0 defaults VCORE to 1.5 V, DEFCORE = VCC defaults VCORE to 1.6 V.
DEFMAIN I Defines the default voltage of the VMAIN switching converter. DEFMAIN = 0 defaults VMAIN to 3.0 V, DEFMAIN = VCC defaults VMAIN to 3.3 V.
LOW_PWR I The LOW_PWR pin is used to lower VCORE to the preset voltage in the VDCDC2 register when the processor is in deep sleep mode. Alternatively, VCORE can be disabled in low-power mode if the LP_COREOFF bit is set in the VDCDC2 register. LOW_PWR is ignored if the ENABLE LP bit is not set in the VDCDC1 register. The TPS65012 uses the rising edge of the internal signal formed by a logical AND of LOW_PWR and ENABLE LP to enter low-power mode. TPS65012 is forced out of low-power mode by de-asserting LOW_PWR, by resetting ENABLE LP to 0, by activating the PB_ONOFF pin or by activating the HOT_RESET pin. There are two ways to get the device back into low-power mode: a) toggle the LOW_PWR pin, or b) toggle the low-power bit when the LOW_PWR pin is held high.
PB_ONOFF I PB_ONOFF can be used to exit the low-power mode and return the core voltage to the value before low-power mode was entered. If PB_ONOFF is used to exit the low-power mode, then the low-power mode can be reentered by toggling the LOW_PWR pin or by toggling the low-power bit when the LOW_PWR pin is held high. A 1-MΩ pulldown resistor is integrated in TPS65012. PB_ONOFF is internally de-bounced by the TPS65012. A maskable interrupt is generated when PB_ONOFF is activated.
HOT_RESET I The HOT_RESET pin has a similar functionality to the PB_ONOFF pin. In addition, it generates a reset (MPU_RESET) for the MPU when the VCORE voltage is in regulation. HOT_RESET does not alter any TPS65012 settings unless low-power mode was active, in which case it is exited. A 1-MΩ pullup resistor to VCC is integrated in TPS65012. HOT_RESET is internally de-bounced by the TPS65012.
BATT_COVER I The BATT_COVER pin is used as an early warning that the main battery is about to be removed. BATT_COVER = VCC indicates that the cover is in place, BATT_COVER = 0 indicates that the cover is not in place. TPS65012 generates a maskable interrupt when the BATT_COVER pin goes low. PWRFAIL is also held low when BATT_COVER goes low. This feature may be disabled by tying BATT_COVER permanently to VCC. The TPS65012 shuts down the main and the core converter and sets the LDOs into low-power mode. A 2-MΩ pulldown resistor is integrated in the TPS65012 at the BATT_COVER pin. BATT_COVER is internally de-bounced by the TPS65012.
RESPWRON O RESPWRON is held low while the switching converters (and any LDOs defined as default on) are starting up. It is determined by the state of LDO1's output voltage; when the voltage is higher than the power-good comparator threshold, then RESPWRON is high; when VLDO1 is low then RESPWRON is low. RESPWRON is held low for tn(RESPWRON) seconds after VLDO1 has settled.
MPU_RESET O MPU_RESET can be used to reset the processor if the user activates theHOT_RESET button. The MPU_RESET output is active for t(MPU_nRESET) seconds. It also forces TPS65012 to leave low-power mode. MPU_RESET is also held low as long as RESPWRON is held low.
PWRFAIL O PWRFAIL indicates when VCC < V(UVLO), when the TPS65012 is about to shut down due to an internal overtemperature condition or when BATT_COVER is low. PWRFAIL is also held low as long as RESPWRON is held low.

Figure 30 shows the state diagram for the TPS65012 power sequencing. The charger function is not shown in the state diagram because this function is independent of these states.

TPS65012 ai_diagram_lvs504.gif Figure 30. TPS65012 Power-On State Diagram

7.3.6 System Reset and Control Signals

The RESPWRON signal is used as a global reset for the application. It is an open-drain output. The RESPWRON signal is generated according to the power-good comparator linked to VLDO1 and remains low for tn(RESPWRON) seconds after VLDO1 has stabilized. When RESPWRON is low, PWRFAIL, MPU_RESET and INT are also held low.

If the output voltage of LDO1 is less than 90% of its nominal value, as RESPWRON is generated, and if the output voltage of LDO1 is programmed to a higher value, which causes the output voltage to fall out of the 90% window, then a RESPWRON signal is generated.

The PWRFAIL signal indicates when VCC < UVLO or when the TPS65012 junction temperature has exceeded a reliable value or if BATT_COVER is taken low. This open-drain output can be connected at a fast interrupt pin for immediate attention by the application processor. All supplies are disabled t(uvlo), t(overtemp) or t(batt_cover) seconds after PWRFAIL has gone low, giving time for the application processor to shut down cleanly.

The BATT_COVER function detects whether the battery cover is in place or not. If the battery cover is removed, the TPS65012 generates a warning to the processor that the battery is likely to be removed and that it may be prudent to shut down the system. If not required, this feature may be disabled by connecting the BATT_COVER pin to the VCC pin. BATT_COVER is de-bounced internally. Typical de-bounce time is 56 ms. BATT_COVER has an internal 2-MΩ pulldown resistor.

The HOT_RESET input is used to generate an MPU_RESET signal for the application processor. The HOT_RESET pin could be connected to a user-activated button in the application. It can also be used to exit low-power mode. In this case, the TPS65012 waits until the VCORE voltage has stabilized before generating the MPU_RESET pulse. The MPU_RESET pulse is active low for t(mpu_nreset) seconds. HOT_RESET has an internal 1-MΩ pullup resistor to VCC.

The PB_ONOFF input can be used to exit LOW-POWER MODE. It is typically driven by a user-activated push-button in the application. Both HOT_RESET and PB_ONOFF are de-bounced internally by the TPS65012. Typical de-bounce time is 56 ms. PB_ONOFF has an internal 1-MΩ pulldown resistor.

PB_ONOFF, BATT_COVER and UVLO events also cause a normal, maskable interrupt to be generated and are noted in the REGSTATUS register.

7.3.7 Vibrator Driver

The VIB open-drain output is provided to drive a vibrator motor, controlled via the serial interface register VDCDC2. It has a maximum dropout of 0.5 V at 100-mA load. Typically, an external resistor is required to limit the motor current and a freewheel diode to limit the VIB overshoot voltage at turnoff.

7.4 Device Functional Modes

7.4.1 TPS65012 Power States Description

7.4.1.1 State 1: No Power

No batteries are connected to the TPS65012. When main power is applied, the RESPWRON, PWRFAIL, INT, and MPU_RESET signals are held low. When BATT_COVER goes high (de-bounced internally by the TPS65012), indicating that the battery cover has been put in place and if VCC > UVLO, the power supplies are ramped in the sequence defined by PS_SEQ. RESPWRON, PWRFAIL, INT, and MPU_RESET are released when the RESPWRON timer has timed out after tn(RESPWRON) seconds. If VCC remains valid and no OVERTEMP condition occurs, then the TPS65012 arrives in State 2: ON. The TPS65012 keeps the bandgap reference and UVLO comparator active for approximately 10 ms after BATT_COVER has been de-bounced going high. VCC must be greater than the UVLO threshold during this time, or else the TPS65012 proceeds to State 4: WAIT, where all supplies are powered down.

7.4.1.2 State 2: ON

In this state, TPS65012 is powered up and ready to go. The switching converters can have their output voltages programmed. The LDOs can be enabled, disabled, or reprogrammed. TPS65012 can exit this state due to an overtemperature condition, an undervoltage condition at VCC, by BATT_COVER going low, or by the processor programming LOW-POWER MODE, or WAIT. State 2 is left temporarily if the user activates the HOT_RESET pin.

7.4.1.3 State 3: Low-Power Mode

This state is entered via the processor setting the ENABLE LP bit in the serial interface (see the VDCDC1 register) and then raising the LOW_PWR pin. The TPS65012 actually uses the rising edge of the internal signal formed by a logical AND of the LOW_PWR and ENABLE LP signals to enter low-power mode. The VMAIN switching converter remains active, but the VCORE converter may be disabled in low-power mode via the serial interface by setting the LP_COREOFF bit in the VDCDC2 register. If left enabled, the VCORE voltage is set to the value predefined by the CORELP0/1 bits in the VDCDC2 register. The LDO1OFF/nSLP and LDO2OFF/nSLP bits in the VREGS1 register determine whether the LDOs are turned off or put in a reduced power mode (current limits are reduced and the transient speed-up circuitry disabled in order to minimize quiescent current) in low-power mode. All TPS65012 features remain addressable via the serial interface. TPS65012 can normally exit this state either by the processor deasserting the LOW_POWER pin, or by the user activating the HOT_RESET pin or the PB_ONOFF pin. If both LDOs are set to be disabled in low-power mode, then this mode must be left by activating the HOT_RESET pin or the PB_ONOFF pin. An undervoltage condition at VCC, or an OVERTEMP condition, or BATT_COVER going low forces the TPS65012 to transit to State 4: WAIT.

7.4.1.4 State 4: Shutdown

WAIT mode can be entered from any of the above states when fault conditions exist:

  1. From State 1 when a discharged battery is applied.
  2. From States 2 and 3 if an OVERTEMP condition exists.
  3. If VCC drops below the UVLO threshold.
  4. If BATT_COVER goes low indicating that the battery is about to be removed.

WAIT mode can also be initiated by the processor. This is done by setting the ENABLE SUPPLY bit (VDCDC1 register) low, the ENABLE LP bit (also VDCDC1 register) high, and then raising the low-power pin. When this occurs, the VMAIN and VCORE converters are powered down according to PS_SEQ. The LDOs can remain enabled in reduced quiescent current operation or be programmed to turn off in WAIT mode. If all supplies are disabled and both VMAIN and VCORE are discharged close to ground, then the voltage reference circuitry is disabled and the serial interface registers reset to their default values. WAIT mode is left by activating either the PB_ONOFF or HOT_RESET pins. For this to be successful, the voltage at VCC must exceed the UVLO threshold, and the BATT_COVER pin must be high.

Table 4 indicates the typical quiescent current consumption in each power state.

Table 4. TPS65012 Typical Current Consumption

STATE TOTAL QUIESCENT
CURRENT
QUIESCENT CURRENT BREAKDOWN
1 0
2 30 µA-70 µA VMAIN (12 µA) + VCORE (12 µA) + LDOs (20 µA each, max 2) + UVLO + reference + PowerGood
3 30 µA-55 µA VMAIN (12 µA) + VCORE (12 µA) + LDOs (10 µA each, max 2) + UVLO + reference + PowerGood
4 13 µA UVLO + reference circuitry
TPS65012 ai_st1-st2_lvs504.gif Figure 31. State 1 to State 2 Transition (PS_SEQ=0, VCC > VUVLO + HYST)

Valid for LDO1 supplied from VMAIN as described in Application Information.

If 2.4 ms after application, VCC is still below the default UVLO threshold (3.425 V for VCC rising), then start-up is as shown in Figure 32.

TPS65012 ai_st1-to-4_lvs504.gif Figure 32. State 1 to State 4 to State 2 Transition (Power-Up Behavior When VCC Ramp is Longer Than 2.4 ms)

Valid for LDO1 supplied from VMAIN as described in Application Information.

TPS65012 ai_state1to4_lvs504.gif Figure 33. State 2 to State 4 Transition

Valid for LDO1 supplied from VMAIN as described in Application Information.

TPS65012 ai_state23_lvs504.gif Figure 34. State 2 to State 3 Transition. VCORE Lowered, LDO2 Disabled. Subsequent State 3 to State 2 Transition When LOW-POWER Is De-Asserted.

NOTE

If both LDOs are turned off in low-power mode, the low-power mode can only be exited by activating HOT_RESET or PB_ONOFF.

TPS65012 ai_state32PB_lvs149.gif Figure 35. State 3 to State 2 Transition. PB_ONFF Activated (See Interrupt Management for INT Behavior)
TPS65012 ai_state32HT_lvs149.gif Figure 36. State 3 to State 2 Transition (HOT_RESET Activated, See Interrupt Management for INT Behavior)
TPS65012 ai_state2to4_lvs504.gif Figure 37. State 2 to State 4 Transition

7.5 Programming

7.5.1 LED2 Output

The LED2 output can be programmed in the same way as the PG output to blink or to be permanently on or off. The LED2_ON and LED2_PER registers are used to control the blink rate. For both PG and LED2, the minimum blink-on time is 10 ms. This can be increased in 127 10-ms steps to 1280 ms. For both PG and LED2, the minimum blink period is 100 ms. This can be increased in 127 100-ms steps to 12800 ms.

7.5.2 Interrupt Management

The open-drain INT pin is used to combine and report all possible conditions via a single pin. Battery and chip temperature faults, precharge timeout, charge timeout, taper timeout, and termination current are each capable of setting INT low, i.e., active. INT can also be activated if any of the regulators are below the regulation threshold. Interrupts can also be generated by any of the GPIO pins programmed to be inputs. These inputs can be programmed to generate an interrupt either at the rising or falling edge of the input signal. It is possible to mask an interrupt from any of these conditions individually by setting the appropriate bits in the MASK1, MASK2, or MASK3 registers. By default, all interrupts are masked. Interrupts are stored in the CHGSTATUS, REGSTATUS, and DEFGPIO registers in the serial interface. CHGSTATUS and REGSTATUS interrupts are acknowledged by reading these registers. If a 1 is present in any location, then the TPS65012 automatically sets the corresponding bit in the ACKINT1 or ACKINT2 registers and releases the INT pin. The ACKINT register contents are self-clearing when the condition, which caused the interrupt, is removed. The applications processor should not normally need to access the ACKINT1 or ACKINT2 registers.

Interrupt events are always captured; thus when an interrupt source is unmasked, INT may immediately go active due to a previous interrupt condition. This can be prevented by first reading the relevant STATUS register before unmasking the interrupt source.

If an interrupt condition occurs, then the INT pin is set low. The CHGSTATUS, REGSTATUS, and DEFGPIO registers should be read. Bit positions containing a 1 (or possibly a 0 in DEFGPIO) are noted by the CPU and the corresponding situation resolved. The reading of the CHGSTATUS and REGSTATUS registers automatically acknowledges any interrupt condition in those registers and blocks the path to the INT pin from the relevant bit(s). No interrupt should be missed during the read process because this process starts by latching the contents of the register before shifting them out at SDAT. Once the contents have been latched (takes a couple of nanoseconds), the register is free to capture new interrupt conditions. Hence, the probability of missing anything is, for practical purposes, zero.

The following describes how registers 0x01 (CHGSTATUS) and 0x02 (REGSTATUS) are handled:

  • CHGSTATUS(5,0) are positive edge set. Read of set CHGSTATUS(5,0) bits sets ACKINT1(5,0) bits.
  • CHGSTATUS(7-6,4-1) are level set. Read of set CHGSTATUS(7-6,4-1) bits sets ACKINT1(7-6,4-1) bits.
  • CHGSTATUS(5,0) clear when input signal low, and ACKINT1(5,0) bits are already set.
  • CHGSTATUS(7-6,4-1) clear when input signal is low.
  • ACKINT1(7-0) clear when CHGSTATUS(7-0) is clear.
  • REGSTATUS(7-5) are positive edge set. Read of set REGSTATUS(7-5) bits sets ACKINT2(7-5) bits.
  • REGSTATUS(3-0) are level set. Read of set REGSTATUS(3-0) bits sets ACKINT2(3-0) bits.
  • REGSTATUS(7-5) clear when input signal low, and ACKINT1(7-5) bit are already set.
  • REGSTATUS(3-0) clear when input signal is low.
  • ACKINT2(7-0) clear when REGSTATUS(7-0) is clear.

The following describes the function of the 0x05 (ACKINT1) and 0x06 (ACKINT2) registers. These are not usually written to by the CPU since the TPS65012 internally sets/clears these registers:

  • ACKINT1(7:0) - Bit is set when the corresponding CHGSTATUS set bit is read via I2C.
  • ACKINT1(7:0) - Bit is cleared when the corresponding CHGSTATUS set bit clears.
  • ACKINT2(7:0) - Bit is set when the corresponding REGSTATUS set bit is read via I2C.
  • ACKINT2(7:0) - Bit is cleared when the corresponding REGSTATUS set bit clears.
  • ACKINT1(7:0) - a bit set masks the corresponding CHGSTATUS bit from INT.
  • ACKINT2(7:0) - a bit set masks the corresponding REGSTATUS bit from INT.

The following describes the function of the 0x03 (MASK1), 0x04 (MASK2) and 0x0F (MASK3) registers:

  • MASK1(7:0) - a bit set in this register masks CHGSTATUS from INT.
  • MASK2(7:0) - a bit set in this register masks REGSTATUS from INT.
  • MASK3(7:4) - a bit set in this register detects a rising edge on GPIO.
  • MASK3(7:4) - a bit cleared in this register detects a falling edge on GPIO.
  • MASK3(3:0) - a bit set in this register clears GPIO detect signal from INT.

GPIO interrupts are located by reading the 0x10 (DEFGPIO) register. The application CPU stores, or can read from DEFGPIO<7:4>, which GPIO is set to input or output. This information together with the information on which edge the interrupt was generated (the CPU either knows this or can read it from MASK3<7:4>) determines whether the CPU is looking for a 0 or a 1 in DEFGPIO<3:0>. A GPIO interrupt is blocked from the INT pin by setting the relevant MASK3<3:0> bit; this must be done by the CPU; there is no auto-acknowledge for the GPIO interrupts.

7.5.3 Serial Interface

The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to 400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as VCC remains above 2 V. The TPS65012 has a 7-bit address with the LSB set by the IFLSB pin; this allows the connection of two devices with the same address to the same bus. The 6 MSBs are 100100. Attempting to read data from register addresses not listed in this section results in FFh being read out.

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS65012 device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS65012 device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS65012 device must leave the data line high to enable the master to generate the stop condition.

TPS65012 ai_bit_lvs149.gif Figure 38. Bit Transfer on the Serial Interface
TPS65012 ai_st_stop_lvs149.gif Figure 39. START and STOP Conditions
TPS65012 ai_write_dev_lvs149.gif Figure 40. Serial Interface WRITE to TPS65012 Device
TPS65012 ai_read_proA_lvs149.gif Figure 41. Serial Interface READ From TPS65012: Protocol A
TPS65012 ai_read_proB_lvs149.gif Figure 42. Serial Interface READ From TPS65012: Protocol B

7.6 Register Maps

7.6.1 CHGSTATUS Register (Address: 01h—Reset: 00h)

Table 5. CHGSTATUS Register

CHGSTATUS B7 B6 B5 B4 B3 B2 B1 B0
Bit Name USB charge AC charge Thermal
Suspend
Term Current Taper Timeout Chg Timeout Prechg Timeout BattTemp
error
Default 0 0 0 0 0 0 0 0
Read/write R R R R R/W R/W R/W R/W

The CHGSTATUS register contents indicate the status of charge.

Bit 7 USB charge:
0 = inactive.
1 = USB source is present and in the range valid for charging. B7 remains active as long as the charge source is present.
Bit 6 AC charge:
0 = wall plug source is not present and/or not in the range valid for charging.
1 = wall plug source is present and in the range valid for charging. B6 remains active as long as the charge source is present.
Bit 5 Thermal suspend:
0 = charging is allowed.
1 = charging is momentarily suspended due to excessive power dissipation on chip.
Bit 4 Term current:
0 = charging, charge termination current threshold has not been crossed.
1 = charge termination current threshold has been crossed and charging has been stopped. This can be due to a battery reaching full capacity or to a battery removal condition.
Bit 3-1 Prechg Timeout, Chg Timeout, Taper Timeout:
0 = charging
1 = one of the timers has timed out and charging has been terminated.
Bit 0 BattTemp error: Battery temperature error
0 = battery temperature is inside the allowed range and charging is allowed.
1 = battery temperature is outside of the allowed range and charging is suspended.

B1-4 may be reset via the serial interface in order to force a reset of the charger. Any attempt to write to B0 and B5-7 is ignored. A 1 in B<7:0> sets the INT pin active unless the corresponding bit in the MASK register is set.

7.6.2 REGSTATUS Register (Address: 02h—Reset: 00h)

Table 6. REGSTATUS Register

REGSTATUS B7 B6 B5 B4 B3 B2 B1 B0
Bit name PB_ONOFF BATT_COVER UVLO PGOOD LDO2 PGOOD LDO1 PGOOD MAIN PGOOD CORE
Default 0 0 0 0 0 0 0 0
Read/write R R R R R R R R
Bit 7 PB_ONOFF:
0 = inactive
1 = user activated the PB_ONOFF switch to request that all rails are shut down
Bit 6 BATT_COVER:
0 = BATT_COVER pin is high.
1 = BATT_COVER pin is low.
Bit 5 UVLO:
0 = voltage at the VCC pin above UVLO threshold.
1 = voltage at the VCC pin has dropped below the UVLO threshold.

Bit 4 - not implemented

Bit 3 PGOOD LDO2:
0 = LDO2 output in regulation, or LDO2 is disabled with VREGS1<7> =0.
1 = LDO2 output out of regulation.
Bit 2 PGOOD LDO1:
0 = LDO1 output in regulation, or LDO1 is disabled with VREGS1<3> =0.
1 = LDO1 output out of regulation.
Bit 1 PGOOD MAIN:
0 = Main converter output in regulation.
1 = Main converter output out of regulation.
Bit 0 PGOOD CORE:
0 = Core converter output in regulation.
1 = Core converter output out of regulation register, or VDCDC2<7> =1 in low-power mode.

A rising edge in the REGSTATUS register contents causes INT to be driven low if it is not masked in the MASK2.

7.6.3 MASK1 Register (Address: 03h—Reset: FFh)

Table 7. MASK1 Register

MASK1 B7 B6 B5 B4 B3 B2 B1 B0
Bit name Mask USB Mask AC Mask Thermal
Suspend
Mask Term Mask Taper Mask Chg Mask Prechg Mask BattTemp
Default 1 1 1 1 1 1 1 1
Read/write R/W R/W R/W R/W R/W R/W R/W R/W

The MASK1 register is used to mask all or any of the conditions in the corresponding CHGSTATUS<7:0> positions being indicated at the INT pin. Default is to mask all.

7.6.4 MASK2 Register (Address: 04h—Reset: FFh)

Table 8. MASK2 Register

MASK2 B7 B6 B5 B4 B3 B2 B1 B0
Bit name Mask PB_ONOFF Mask BATT_COVER Mask UVLO Mask PGOOD LDO2 Mask PGOOD LDO1 Mask PGOOD MAIN Mask PGOOD CORE
Default 1 1 1 1 1 1 1
Read/write R/W R/W R/W R/W R/W R/W R/W R/W

The MASK2 register is used to mask all or any of the conditions in the corresponding REGSTATUS<7:0> positions being indicated at the INT pin. Default is to mask all.

7.6.5 ACKINT1 Register (Address: 05h—Reset: 00h)

Table 9. ACKINT1 Register

ACKINT1 B7 B6 B5 B4 B3 B2 B1 B0
Bit name Ack USB Ack AC Ack Thermal Shutdown Ack Term Ack Taper Ack Chg Ack Prechg Ack BattTemp
Default 0 0 0 0 0 0 0 0
Read/write R R R R R R R R

The ACKINT1 register is internally used to acknowledge any of the interrupts in the corresponding CHGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT pin, and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes high, else it remains low. A 1 at any position in ACKINT1 is automatically cleared when the corresponding interrupt condition in CHGSTATUS is removed. The application processor should not normally need to access the ACKINT1 register.

7.6.6 ACKINT2 Register (Address: 06h—Reset: 00h)

Table 10. ACKINT2 Register

ACKINT2 B7 B6 B5 B4 B3 B2 B1 B0
Bit name and function Ack PB_ONOFF Ack BATT_
COVER
Ack UVLO Ack PGOOD LDO2 Ack PGOOD LDO1 Ack PGOOD MAIN Ack PGOOD CORE
Default 0 0 0 0 0 0 0 0
Read/write R R R R R R R R

The ACKINT2 register is internally used to acknowledge any of the interrupts in the corresponding REGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes high, else it remains low. A 1 at any position in ACKINT2 is automatically cleared when the corresponding interrupt condition in REGSTATUS is removed. The application processor should not normally need to access the ACKINT2 register.

7.6.7 CHGCONFIG Register Address: 07h—Reset: 1Bh

Table 11. CHGCONFIG Register

CHGCONFIG B7 B6 B5 B4 B3 B2 B1 B0
Bit name POR Charger Reset Fast Charge Timer + Taper Timer Enabled MSB Charge Current LSB Charge Current USB / 100 mA 500 mA USB Charge Allowed Charge
Enable
Default 0 0 0 1 1 0 1 1
Read/write R/W R/W R/W R/W R/W R/W R/W R/W

The CHGCONFIG register is used to configure the charger.

Bit 7 POR:
0 = Tn(RESPWRON) duration typically 1000 ms (+/-25%)
1 = Tn(RESPWRON) duration typically 69 ms (+/-25%)
Bit 6 Charger Reset: clears all the timers in the charger and forces a restart of the charge algorithm.
0 = Normal operation
1 = Charger is in reset.

This bit must be set, and then reset via the serial interface.

Bit 5 Fast Charge Timer + Taper Timer Enabled:
0 = fast charge and taper timers disabled (default).
1 = enables the fast charge and taper times.
Bit 4, Bit 3 MSB/LSB Charge Current:
Used to set the constant current in the current regulation phase.

Table 12. Charge Current Settings

B4:B3 CHARGE CURRENT RATE
11 Maximum current set by the external resistor at the ISET pin
10 75% of maximum
01 50% of maximum
00 32% of maximum
Bit 2 USB 100 mA / 500 mA:
0 = sets the USB charging current to max 100 mA.
1 = sets the USB charging current to max 500 mA. B2 is ignored if B1=0.
Bit 1 USB charge allowed:
0 = prevents any charging from the USB input.
1 = charging from the USB input is allowed.
Bit 0 Charge enable:
0 = charging is not allowed.
1 = charger is free to charge from either of the two input sources. If both sources are present and valid, the TPS65012 charges from the ac source.

7.6.8 LED1_ON Register (Address: 08h—Reset: 00h)

Table 13. LED1_ON Register

LED1_ON B7 B6 B5 B4 B3 B2 B1 B0
Bit name PG1 LED1 ON6 LED1 ON5 LED1 ON4 LED1 ON3 LED1 ON2 LED1 ON1 LED1 ON 0
Default 0 0 0 0 0 0 0 0
Read/write R/W R/W R/W R/W R/W R/W R/W R/W

The LED1_ON and LED1_PER registers can be used to take control of the PG open-drain output normally controlled by the charger.

Bit 7 - PG1: Control of the PG pin is determined by PG1 and PG2 according to the table under LED1_PER register

Bit 6 - BIT 0 LED1_ON<6:0> are used to program the on-time of the open-drain output transistor at the PG pin. The minimum on-time is typically 10 ms and one LSB corresponds to a 10-ms step change in the on-time.

7.6.9 LED1_PER Register (Address: 09h—Reset: 00h)

Table 14. LED1_PER Register

LED1_PER B7 B6 B5 B4 B3 B2 B1 B0
Bit name PG2 LED1 PER6 LED1 PER5 LED1 PER4 LED1 PER3 LED1 PER2 LED1 PER1 LED1 PER 0
Default 0 0 0 0 0 0 0 0
Read/write R/W R/W R/W R/W R/W R/W R/W R/W

Bit 7 - PG2: Control of the PG pin is determined by PG1 and PG2 according to the following table.

Table 15. PG Open-Drain Output Settings

PG1 PG2 BEHAVIOR OF PG OPEN-DRAIN OUTPUT
0 0 Under charger control (default) (1)
0 1 Blink
1 0 Off
1 1 Always On
(1) PG is low if either USB or AC are in the valid range for battery charging.

Bit 6-Bit 0 LED1_PER<6:0> are used to program the time period of the open-drain output transistor at the PG pin. The minimum period is typically 100 ms and one LSB corresponds to a 100-ms step change in the period.

7.6.10 LED2_ON Register (Address: 0Ah—Reset: 00h)

Table 16. LED2_ON Register

LED2_ON B7 B6 B5 B4 B3 B2 B1 B0
Bit name LED21 LED2 ON6 LED2 ON5 LED2 ON4 LED2 ON3 LED2 ON2 LED2 ON1 LED2 ON0
Default 0 0 0 0 0 0 0 0
Read/write R/W R/W R/W R/W R/W R/W R/W R/W

The LED2_ON and LED2_PER registers are used to control the LED2 open-drain output.

Bit 7 LED22: Control is determined by LED21 and LED22 according to the table under LED2_PER register.

Bit 6-Bit 0 LED2_ON<6:0> are used to program the on-time of the open-drain output transistor at the LED2 pin. The minimum on-time is typically 10 ms and one LSB corresponds to a 10-ms step change in the on-time.

7.6.11 LED2_PER (Register Address: 0Bh—Reset: 00h)

Table 17. LED2_PER

LED2_PER B7 B6 B5 B4 B3 B2 B1 B0
Bit name LED22 LED2 PER6 LED2 PER5 LED2 PER4 LED2 PER3 LED2 PER2 LED2 PER1 LED2 PER 0
Default 0 0 0 0 0 0 0 0
Read/write R/W R/W R/W R/W R/W R/W R/W R/W

Bit 7 LED22: Control is determined by LED21 and LED22 according to the table.

Bit 6-Bit 0 - LED2_PER<6:0> are used to program the on-time of the open-drain output transistor at the LED2 pin. The minimum on-time is typically 100 ms and one LSB corresponds to a 100-ms step change in the on-time.

Table 18. LED2 Open-Drain Output Setting

LED21 LED22 BEHAVIOR OF LED2 OPEN-DRAIN OUTPUT
0 0 Off
0 1 Blink
1 0 Off
1 1 Always On

7.6.12 VDCDC1 Register (Address: 0Ch—Reset: 72h/73h)

Table 19. VDCDC1 Register

VDCDC1 B7 B6 B5 B4 B3 B2 B1 B0
Bit name FPWM UVLO1 UVLO0 ENABLE SUPPLY ENABLE LP MAIN DISCHARGE MAIN1 MAIN0
Default 0 1 1 1 0 0 1 DEFMAIN
Read/write R/W R/W R/W R/W R/W R/W R/W R/W

The VDCDC1 register is used to program the VMAIN switching converter.

Bit 7 FPWM: forced PWM mode for DC-DC converters.
0 = MAIN and the CORE DC-DC converter are allowed to switch into PFM mode.
1 = MAIN and the CORE DC-DC converter operate with forced fixed frequency PWM mode and are not allowed to switch into PFM mode at light load.

Bit 6-Bit 5 - UVLO<1:0>: The undervoltage threshold voltage is set by UVLO1 and UVLO0 according to Table 20.

Table 20. UVLO Settings

UVLO1 UVLO0 VUVLO
0 0 2.5 V
0 1 2.75 V
1 0 3.0 V
1 1 3.25 V (reset)
Bit 4 ENABLE SUPPLY:
0 = Disable CORE and MAIN converters when ENABLE LP = 1 and LOW PWR pin goes high.
1 = CORE and MAIN converters remain enabled.
Bit 3 ENABLE LP:
0 = disables the low-power function of the LOW_PWR pin.
1 = enables the low-power function of the LOW_PWR pin.
Bit 2 MAIN DISCHARGE:
0 = Disable the active discharge of the VMAIN output capacitor.
1 = Enable the active discharge of the VMAIN output capacitor when the converter is disabled.

Bit 1-Bit 0 - MAIN<1:0>: The VMAIN converter output voltages are set according to Table 21, with the reset in bold set by the DEFMAIN pin. The default voltage can subsequently be overwritten via the serial interface after start-up.

Table 21. MAIN Settings

MAIN1 MAIN0 VMAIN
0 0 2.5 V
0 1 2.75 V
1 0 3.0 V
1 1 3.3 V

7.6.13 VDCDC2 Register (Address: 0Dh—Reset: 68h/78h)

Table 22. VDCDC2 Register

VDCDC2 B7 B6 B5 B4 B3 B2 B1 B0
Bit name LP_COREOFF CORE2 CORE1 CORE0 CORELP1 CORELP0 VIB CORE
DISCHARGE
Default 0 1 1 DEFCORE 1 0 0 0
Read/write R/W R/W R/W R/W R/W R/W R/W R/W

The VDCDC2 register is used to program the VCORE switching converter output voltage. It is programmable in 8 steps between 0.85 V and 1.6 V. The reset is governed by the DEFCORE pin; DEFCORE=0 sets an output voltage of 1.5 V. DEFCORE=1 sets an output voltage of 1.6 V.

Bit 7 LP_COREOFF:
0 = VCORE converter is enabled in low-power mode.
1 = VCORE converter is disabled in low-power mode.

Bit 6-Bit 4 - CORE<2:0>: The following table shows all possible values of VCORE. The reset can subsequently be overwritten via the serial interface after start-up.

Table 23. CORE Settings

CORE2 CORE1 CORE0 VCORE
0 0 0 0.85 V
0 0 1 1.0 V
0 1 0 1.1 V
0 1 1 1.2 V
1 0 0 1.3 V
1 0 1 1.4 V
1 1 0 1.5 V
1 1 1 1.6 V

Bit 3-Bit 2 - CORELP<1:0>: CORELP1 and CORELP0 can be used to set the VCORE voltage in low-power mode. In low-power mode, CORE2 is effectively '0'; CORE1 and CORE0 take on the values programmed at CORELP1 and CORELP0, default '10' giving VCORE = 1.1 V as default in low-power mode. When low-power mode is exited, VCORE reverts to the value set by CORE2, CORE1, and CORE0.

Bit 1 VIB:
0 = Disables the open-drain VIB output transistor.
1 = Enables the open-drain VIB output transistor to drive the vibrator motor.
Bit 0 CORE DISCHARGE:
0 = Disable the active discharge of the VCORE output capacitor.
1 = Enable the active discharge of the VCORE output capacitor when the converter is disabled.

7.6.14 VREGS1Register (Address: 0Eh—Reset: 88h)

Table 24. VREGS1Register

VREGS1 B7 B6 B5 B4 B3 B2 B1 B0
Bit name LDO2 enable LDO2 OFF / nSLP LDO21 LDO20 LDO1 enable LDO1 OFF / nSLP LDO11 LDO10
Default 1 0 0 0 1 0 0 0
Read/write R/W R/W R/W R/W R/W R/W R/W R/W

The VREGS1 register is used to program and enable LDO1 and LDO2 and to set their behavior when low-power mode is active. The LDO output voltages can be set either on the fly, while the relevant LDO is disabled, or simultaneously when the relevant enable bit is set. Note that both LDOs are per default ON.

Bit 7-Bit 6 - The function of the LDO2 enable and LDO2 OFF/nSLP bits is shown in Table 25. See the power-on sequencing section for details of low-power mode.

Table 25. LDO2 Enable and LDO2 OFF/nSLP Functions

LDO2 ENABLE LDO2 OFF / nSLP LDO STATUS IN NORMAL MODE LDO STATUS IN LOW-POWER MODE
0 X OFF OFF
1 0 ON, full power ON, reduced power / performance
1 1 ON, full power OFF

Bit 5-Bit 4 - LDO2<1:0>: LDO2 has a default output voltage of 1.8 V. If so desired, this can be changed at the same time as it is enabled via the serial interface.

Table 26. LDO2 Settings

LDO21 LDO20 VLDO2
0 0 1.8 V
0 1 2.5 V
1 0 2.75 V
1 1 3.0 V

Bit 3-Bit 2 - The function of the LDO1 enable and LDO1 OFF/nSLP bits is shown in the following table. See the power-on sequencing section for details of low-power mode. Note that programming LDO1 to a higher voltage may force a system power-on reset if the increase is in the 10% or greater range.

Table 27. LDO1 Enable and LDO1 OFF/nSLP Functions

LDO1 ENABLE LDO1 OFF / nSLP LDO STATUS IN NORMAL MODE LDO STATUS IN LOW-POWER MODE
0 X OFF OFF
1 0 ON, full power ON, reduced power / performance
1 1 ON, full power OFF

Bit 1-Bit 0 - LDO1<1:0>: The LDO1 output voltage is per default set externally. If so desired, this can be changed via the serial interface. The adjustable range is 0.9 V to VINLDO1.

Table 28. LDO1 Settings

LDO11 LDO10 VLDO1
0 0 ADJ
0 1 2.5 V
1 0 2.75 V
1 1 3.0 V

7.6.15 MASK3 Register (Address: 0Fh—Reset: 00h)

Table 29. MASK3 Register

MASK3 B7 B6 B5 B4 B3 B2 B1 B0
Bit name Edge trigger GPIO4 Edge trigger GPIO3 Edge trigger GPIO2 Edge trigger GPIO1 Mask GPIO4 Mask GPIO3 Mask GPIO2 Mask GPIO1
Default 0 0 0 0 0 0 0 0
Read/write R/W R/W R/W R/W R/W R/W R/W R/W

The MASK3 register must be considered when any of the GPIO pins are programmed as inputs.

Bit 7-Bit 4 edge trigger GPIO<4:1>: determine whether the respective GPIO generates an interrupt at a rising or a falling edge
0 = falling edge triggered.
1 = rising edge triggered.

Bit 3-Bit 0 - Mask GPIO<4:1>: can be used to mask the corresponding interrupt. Default is unmasked (MASK3<0:3> =0).

7.6.16 DEFGPIO Register Address: (10h—Reset: 00h)

Table 30. DEFGPIO Register

DEFGPIO B7 B6 B5 B4 B3 B2 B1 B0
Bit name IO4 IO3 IO2 IO1 Value GPIO4 Value GPIO3 Value GPIO2 Value GPIO1
Default 0 0 0 0 0 0 0 0
Read/write R/W R/W R/W R/W R/W R/W R/W R/W

The DEFGPIO register is used to define the GPIO pins to be either input or output.

Bit 7-Bit 4 IO<4:1>:
0 = sets the corresponding GPIO to be an input.
1 = sets the corresponding GPIO to be an output.
Bit 3-Bit 0 Value GPIO<4:1>: If a GPIO is programmed to be an output, then the signal output is determined by the corresponding bit. The output circuit for each GPIO is an open-drain NMOS requiring an external pullup resistor.
1 = activates the relevant NMOS, hence forcing a logic low signal at the GPIO pin.
0 = turns the open-drain transistor OFF, hence the voltage at the GPIO pin is determined by the voltage to which the pullup resistor is connected

If a particular GPIO is programmed to be an input, then the contents of the relevant bit in B3-0 is defined by the logic level at the GPIO pin. A logic low forces a 0 and a logic high forces a 1. If a GPIO is programmed to be an input, then any attempt to write to the relevant bit in B3-0 is ignored.