SLVS607D September   2005  – January 2016 TPS65020

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3
    7. 7.7  Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
    8. 7.8  Electrical Characteristics: VDCDC1 Step-Down Converter
    9. 7.9  Electrical Characteristics: VDCDC2 Step-Down Converter
    10. 7.10 Electrical Characteristics: VDCDC3 Step-Down Converter
    11. 7.11 Timing Requirements
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VRTC Output and Operation With or Without Backup Battery
      2. 8.3.2  Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      3. 8.3.3  Power Save Mode Operation
      4. 8.3.4  Low Ripple Mode
      5. 8.3.5  Soft-Start
      6. 8.3.6  100% Duty Cycle Low-Dropout Operation
      7. 8.3.7  Active Discharge When Disabled
      8. 8.3.8  Power-Good Monitoring
      9. 8.3.9  Low-Dropout Voltage Regulators
      10. 8.3.10 Undervoltage Lockout
      11. 8.3.11 Power-Up Sequencing
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 System Reset + Control Signals
        1. 8.5.1.1 PB_IN and PB_OUT
        2. 8.5.1.2 Interrupt Management and the INT Pin
      2. 8.5.2 Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1 VERSION Register Address: 00h (Read Only)
      2. 8.6.2 PGOODZ Register Address: 01h (Read Only)
      3. 8.6.3 MASK Register Address: 02h (Read and Write), Default Value: C0h
      4. 8.6.4 REG_CTRL Register Address: 03h (Read and Write), Default Value: FFh
      5. 8.6.5 CON_CTRL Register Address: 04h (Read and Write), Default Value: B0h
      6. 8.6.6 CON_CTRL2 Register Address: 05h (Read and Write), Default Value: 40h
      7. 8.6.7 DEFCORE. Register Address: 06h (Read and Write), Default Value: 14h/1Eh
      8. 8.6.8 DEFSLEW Register Address: 07h (Read and Write), Default Value: 06h
      9. 8.6.9 LDO_CTRL Register Address: 08h (Read and Write), Default Value: 23h
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Voltage Connection
      2. 9.1.2 Unused Regulators
      3. 9.1.3 Implementing a Push-Button On-Off Function Using PB_IN and PB_OUT
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection for the DC-DC Converters
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Output Voltage Selection
        5. 9.2.2.5 VRTC Output
        6. 9.2.2.6 LDO1 and LDO2
        7. 9.2.2.7 TRESPWRON
        8. 9.2.2.8 VCC Filter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Requirements for Supply Voltages Below 3.0 V
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RHA Package
40-Pin VQFN
Top View
TPS65020 pin_out_lvs607.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
SWITCHING REGULATOR SECTION
AGND1 40 Analog ground connection. All analog ground pins are connected internally on the chip.
AGND2 17 Analog ground connection. All analog ground pins are connected internally on the chip.
DEFDCDC1 10 I Input signal indicating default VDCDC1 voltage, 0 = 3 V, 1 = 3.3 V This pin can also be connected to a resistor divider between VDCDC1 and GND. If the output voltage of the DCDC1 converter is set in a range from 0.6 V to VINDCDC1 V
DEFDCDC2 32 I Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 2.5 V This pin can also be connected to a resistor divider between VDCDC2 and GND. If the output voltage of the DCDC2 converter is set in a range from 0.6 V to VINDCDC2 V
DEFDCDC3 1 I Input signal indicating default VDCDC3 voltage, 0 = 1.3 V, 1 = 1.55 V This pin can also be connected to a resistor divider between VDCDC3 and GND. If the output voltage of the DCDC3 converter is set in a range from 0.6 V to VINDCDC3 V
DCDC1_EN 25 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC2_EN 24 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC3_EN 23 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.
L1 7 Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.
L2 35 Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.
L3 4 Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.
PGND1 8 Power ground for VDCDC1 converter
PGND2 34 Power ground for VDCDC2 converter
PGND3 3 Power ground for VDCDC3 converter
PowerPAD™ – Connect the power pad to analog ground
VCC 37 I Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 DC-DC converters. This must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2. Also supplies serial interface block
VDCDC1 9 I VDCDC1 feedback voltage sense input, connect directly to VDCDC1
VDCDC2 33 I VDCDC2 feedback voltage sense input, connect directly to VDCDC2
VDCDC3 2 I VDCDC3 feedback voltage sense input, connect directly to VDCDC3
VINDCDC1 6 I Input voltage for VDCDC1 step-down converter. This must be connected to the same voltage supply as VINDCDC2, VINDCDC3, and VCC.
VINDCDC2 36 I Input voltage for VDCDC2 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC3, and VCC.
VINDCDC3 5 I Input voltage for VDCDC3 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC2, and VCC.
LDO REGULATOR SECTION
LDO_EN 22 I Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs
VBACKUP 15 I Connect the backup battery to this input pin.
VINLDO 19 I I Input voltage for LDO1 and LDO2
VLDO1 20 O Output voltage of LDO1
VLDO2 18 O Output voltage of LDO2
VRTC 16 O Output voltage of the LDO and switch for the real time clock
VSYSIN 14 I Input of system voltage for VRTC switch
CONTROL AND I2C SECTION
HOT_RESET 11 I Push button input used to reboot or wake-up processor through the RESPWRON output pin
INT 28 O Open-drain output
LOW_BAT 21 O Open-drain output of LOW_BAT comparator
LOWBAT_SNS 39 I Input for the comparator driving the LOW_BAT output
PB_IN 12 I/O Push button input debounced and output fed to latch at PB_OUT
PB_OUT 13 I/O Open-drain output of latch driven by PB_IN. Low after power up.
PWRFAIL 31 O Open-drain output. Active-low when PWRFAIL comparator indicates low VBAT condition.
PWRFAIL_SNS 38 I Input for the comparator driving the PWRFAIL output
RESPWRON 27 O Open-drain System reset output
SCLK 30 I Serial interface clock line
SDAT 29 I/O Serial interface data and address
TRESPWRON 26 I Connect the timing capacitor to this pin to set the reset delay time: 1 nF → 100 ms