The TPS65022 is an integrated Power Management IC for applications powered by one Li-Ion or Li-Polymer cell, and which require multiple power rails. The TPS65022 provides three highly efficient, step-down converters targeted at providing the core voltage, peripheral, I/O and memory rails in a processor based system.
All three step-down converters enter a low-power mode at light load for maximum efficiency across the widest possible range of load currents. The TPS65022 also integrates two general-purpose 200-mA LDO voltage regulators, which are enabled with an external input pin. Each LDO operates with an input voltage range between 1.5 V and 6.5 V, allowing them to be supplied from one of the step-down converters or directly from the battery.
The default output voltage of the LDOs can be digitally set to 4 different voltage combinations using the DEFLDO1 and DEFLDO2 pins.
The serial interface can be used for dynamic voltage scaling, masking interrupts, or for disabling, enabling, and setting the LDO output voltages. The interface is compatible with the Fast/Standard mode I2C specification, allowing transfers at up to 400 kHz. The TPS65022 is available in a 40-pin (RHA) VQFN package, and operates over a free-air temperature of –40°C to 85°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS65022 | VQFN (40) | 6.00 mm × 6.00 mm |
Changes from A Revision (July 2006) to B Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
SWITCHING REGULATOR SECTION | |||
AGND1 | 40 | — | Analog ground connection. All analog ground pins are connected internally on the chip. |
AGND2 | 17 | — | Analog ground connection. All analog ground pins are connected internally on the chip. |
DCDC1_EN | 25 | I | VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator. |
DCDC2_EN | 24 | I | VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator. |
DCDC3_EN | 23 | I | VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator. |
DEFDCDC1 | 10 | I | Input signal indicating default VDCDC1 voltage, 0 = 3 V, 1 = 3.3 V. This pin can also be connected to a resistor divider between VDCDC1 and GND. If the output voltage of the DCDC1 converter is set in a range from 0.6 V to VINDCDC1 V. |
DEFDCDC2 | 32 | I | Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 2.5 V. This pin can also be connected to a resistor divider between VDCDC2 and GND. If the output voltage of the DCDC2 converter is set in a range from 0.6 V to VINDCDC2 V. |
DEFDCDC3 | 1 | I | Input signal indicating default VDCDC3 voltage, 0 = 1.3 V, 1 = 1.55 V. This pin can also be connected to a resistor divider between VDCDC3 and GND. If the output voltage of the DCDC3 converter is set in a range from 0.6 V to VINDCDC3 V. |
L1 | 7 | — | Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here. |
L2 | 35 | — | Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here. |
L3 | 4 | — | Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here. |
PGND1 | 8 | — | Power ground for VDCDC1 converter |
PGND2 | 34 | — | Power ground for VDCDC2 converter |
PGND3 | 3 | — | Power ground for VDCDC3 converter |
PowerPAD™ | — | — | Connect the power pad to analog ground. |
VCC | 37 | I | Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 DC-DC converters. This must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2. Also supplies serial interface block |
VDCDC1 | 9 | I | VDCDC1 feedback voltage sense input, connect directly to VDCDC1 |
VDCDC2 | 33 | I | VDCDC2 feedback voltage sense input, connect directly to VDCDC2 |
VDCDC3 | 2 | I | VDCDC3 feedback voltage sense input, connect directly to VDCDC3 |
VINDCDC1 | 6 | I | Input voltage for VDCDC1 step-down converter. This must be connected to the same voltage supply as VINDCDC2, VINDCDC3, and VCC. |
VINDCDC2 | 36 | I | Input voltage for VDCDC2 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC3, and VCC. |
VINDCDC3 | 5 | I | Input voltage for VDCDC3 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC2, and VCC. |
LDO REGULATOR SECTION | |||
DEFLD01 | 12 | I | Digital input, used to set default output voltage of LDO1 and LDO2 |
DEFLD02 | 13 | I | Digital input, used to set default output voltage of LDO1 and LDO2 |
LDO_EN | 22 | I | Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs |
VBACKUP | 15 | I | Connect the backup battery to this input pin. |
VINLDO | 19 | I | I Input voltage for LDO1 and LDO2 |
VLDO1 | 20 | O | Output voltage of LDO1 |
VLDO2 | 18 | O | Output voltage of LDO2 |
VRTC | 16 | O | Output voltage of the LDO/switch for the real time clock |
VSYSIN | 14 | I | Input of system voltage for VRTC switch |
CONTROL AND I2C SECTION | |||
HOT_RESET | 11 | I | Push button input used to reboot or wake-up processor through RESPWRON output pin |
INT | 28 | O | Open-drain output |
LOW_BAT | 21 | O | Open-drain output of LOW_BAT comparator |
LOWBAT_SNS | 39 | I | Input for the comparator driving the LOW_BAT output. |
PWRFAIL | 31 | O | Open-drain output. Active low when PWRFAIL comparator indicates low VBAT condition. |
PWRFAIL_SNS | 38 | I | Input for the comparator driving the PWRFAIL output. |
RESPWRON | 27 | O | Open-drain System reset output |
SCLK | 30 | I | Serial interface clock line |
SDAT | 29 | I/O | Serial interface data/address |
TRESPWRON | 26 | I | Connect the timing capacitor to this pin to set the reset delay time: 1 nF → 100 ms |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VI | Input voltage range on all pins except AGND and PGND pins with respect to AGND | –0.3 | 7 | V |
Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3 | 2000 | mA | ||
Peak current at all other pins | 1000 | mA | ||
TA | Operating free-air temperature | –40 | 85 | °C |
TJ | Maxiumum junction temperature | 125 | °C | |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VCC | Input voltage range step-down convertors (VINDCDC1, VINDCDC2, VINDCDC3); pins need to be tied to the same voltage rail |
2.5 | 6 | V | |
VO | Output voltage range for VDCDC1 step-down convertor(1) | 0.6 | VINDCDC1 | V | |
Output voltage range for VDCDC2 (mem) step-down convertor(1) | 0.6 | VINDCDC2 | |||
Output voltage range for VDCDC3 (core) step-down convertor(1) | 0.6 | VINDCDC3 | |||
VI | Input voltage range for LDOs (VINLDO1, VINLDO2) | 1.5 | 6.5 | V | |
VO | Output voltage range for LDOs (VLDO1, VLDO2) | 1 | VINLDO1-2 | V | |
IO(DCDC2) | Output current at L1 | 1200 | mA | ||
Inductor at L1(2) | 2.2 | 3.3 | μH | ||
CI(DCDC1) | Input capacitor at VINDCDC1 (2) | 10 | μF | ||
CO(DCDC1) | Output capacitor at VDCDC1 (2) | 10 | 22 | μF | |
IO(DCDC2) | Output current at L2 | 1000 | mA | ||
Inductor at L2 (2) | 2.2 | 3.3 | μH | ||
CI(DCDC2) | Input capacitor at VINDCDC2 (2) | 10 | μF | ||
CO(DCDC2) | Output capacitor at VDCDC2 (2) | 10 | 22 | μF | |
IO(DCDC3) | Output current at L3 | 900 | mA | ||
Inductor at L3 (2) | 2.2 | 3.3 | μH | ||
CI(DCDC3) | Input capacitor at VINDCDC3(2) | 10 | μF | ||
CO(DCDC3) | Output capacitor at VDCDC3 (2) | 10 | 22 | μF | |
CI(VCC) | Input capacitor at VCC (2) | 1 | μF | ||
Ci(VINLDO) | Input capacitor at VINLDO (2) | 1 | μF | ||
CO(VLDO1-2) | Output capacitor at VLDO1, VLDO2 (2) | 2.2 | μF | ||
IO(VLDO1-2) | Output current at VLDO1, VLDO2 | 200 | mA | ||
CO(VRTC) | Output capacitor at VRTC (2) | 4.7 | μF | ||
TA | Operating ambient temperature | –40 | 85 | °C | |
TJ | Operating junction temperature | –40 | 125 | °C | |
Resistor from VINDCDC3, VINDCDC2, VINDCDC1 to VCC used for filtering(3) | 1 | 10 | Ω |
THERMAL METRIC(1) | TPS65022 | UNIT | |
---|---|---|---|
RHA (VQFN) | |||
40 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 31.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 18.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 6.6 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 6.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
CONTROL SIGNALS : SCLK, SDAT (input), DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2 | ||||||||
VIH | High level input voltage | Rpullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC | 1.3 | VCC | V | |||
VIL | Low level input voltage | Rpullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC | 0 | 0.4 | V | |||
IH | Input bias current | 0.01 | 0.1 | μA | ||||
CONTROL SIGNALS : HOT_RESET | ||||||||
VIH | High level input voltage | 1.3 | VCC | V | ||||
VIL | Low level input voltage | 0 | 0.4 | V | ||||
IIB | Input bias current | 0.01 | 0.1 | μA | ||||
tdeglitch | Deglitch time at HOT_RESET | 25 | 30 | 35 | ms | |||
CONTROL SIGNALS : LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (output) | ||||||||
VOH | High level output voltage | 6 | V | |||||
VOL | Low level output voltage | IIL = 5 mA | 0 | 0.3 | V | |||
Duration of low pulse at RESPWRON | External capacitor 1 nF | 100 | ms | |||||
ICONST | internal charge and discharge current on pin TRESPWRON | used for generating RESPWRON delay | 1.7 | 2 | 2.3 | μA | ||
TRESPWRON_LOWTH | internal lower comparator threshold on pin TRESPWRON | used for generating RESPWRON delay | 0.225 | 0.25 | 0.275 | V | ||
TRESPWRON_UPTH | internal upper comparator threshold on pin TRESPWRON | used for generating RESPWRON delay | 0.97 | 1 | 1.103 | V | ||
Resetpwron threshold | VRTC falling | –3% | 2.4 | 3% | V | |||
Resetpwron threshold | VRTC rising | –3% | 2.52 | 3% | V | |||
ILK | leakage current | output inactive high | 0.1 | μA | ||||
SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3 | ||||||||
I(q) | Operating quiescent current, PFM | VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V |
All 3 DCDC converters enabled, zero load and no switching, LDOs enabled |
85 | 100 | μA | ||
All 3 DCDC converters enabled, zero load and no switching, LDOs off |
78 | 90 | ||||||
DCDC1 and DCDC2 converters enabled, zero load and no switching, LDOs off |
57 | 70 | ||||||
DCDC1 converter enabled, zero load and no switching, LDOs off |
43 | 55 | ||||||
II | Current into VCC; PWM | VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V |
All 3 DCDC converters enabled and running in PWM, LDOs off |
2 | 3 | mA | ||
DCDC1 and DCDC2 converters enabled and running in PWM, LDOs off |
1.5 | 2.5 | ||||||
DCDC1 converter enabled and running in PWM, LDOs off |
0.85 | 2 | ||||||
I(q) | Quiescent current | All converters disabled, LDOs off, V(VSYSIN) = 0 V |
VCC = 3.6 V, VBACKUP = 3 V | 23 | 33 | μA | ||
VCC = 2.6 V, VBACKUP = 3 V | 3.5 | 5 | ||||||
VCC = 3.6 V, VBACKUP = 0 V | 43 | |||||||
SUPPLY PINS: VBACKUP, VSYSIN, VRTC | ||||||||
I(q) | Operating quiescent current | VBACKUP = 3 V, VSYSIN = 0 V; VCC = 2.6 V, current into VBACKUP |
20 | 33 | μA | |||
I(SD) | Operating quiescent current | VBACKUP < V_VBACKUP, current into VBACKUP | 2 | 3 | μA | |||
VRTC LDO output voltage | VSYSIN = VBACKUP = 0 V, IO = 0 mA | 3 | V | |||||
IO | Output current for VRTC | VSYSIN < 2.57 V and VBACKUP < 2.57 V | 30 | mA | ||||
VRTC short-circuit current limit | VRTC = GND; VSYSIN = VBACKUP = 0 V | 100 | mA | |||||
Maximum output current at VRTC for RESPWRON = 1 |
VRTC > 2.6 V, VCC = 3 V; VSYSIN = VBACKUP = 0 V | 30 | mA | |||||
VO | Output voltage accuracy for VRTC | VSYSIN = VBACKUP = 0 V; IO = 0 mA | –1% | 1% | ||||
Line regulation for VRTC | VCC = VRTC + 0.5 V to 6.5 V, IO = 5 mA | –1% | 1% | |||||
Load regulation VRTC | IO = 1 mA to 30 mA; VSYSIN = VBACKUP = 0 V | –3% | 1% | |||||
Regulation time for VRTC | Load change from 10% to 90% | 10 | μs | |||||
Ilkg | Input leakage current at VSYSIN | VSYSIN < V_VSYSIN | 2 | μA | ||||
rDS(on) of VSYSIN switch | 12.5 | Ω | ||||||
rDS(on) of VBACKUP switch | 12.5 | Ω | ||||||
Input voltage range at VBACKUP(1) | 2.73 | 3.75 | V | |||||
Input voltage range at VSYSIN(1) | 2.73 | 3.75 | V | |||||
VSYSIN threshold | VSYSIN falling | –3% | 2.55 | 3% | V | |||
VSYSIN threshold | VSYSIN rising | –3% | 2.65 | 3% | V | |||
VBACKUP threshold | VBACKUP falling | –3% | 2.55 | 3% | V | |||
VBACKUP threshold | VBACKUP falling | –3% | 2.65 | 3% | V | |||
SUPPLY PIN: VINLDO | ||||||||
I(q) | Operating quiescent current | Current per LDO into VINLDO | 16 | 30 | μA | |||
I(SD) | Shutdown current | Total current for both LDOs into VINLDO, VLDO = 0 V | 0.1 | 1 | μA | |||
VDCDC1 STEP-DOWN CONVERTER | ||||||||
VI | Input voltage range, VINDCDC1 | 2.5 | 6 | V | ||||
IO | Maximum output current | 1200 | mA | |||||
I(SD) | Shutdown supply current in VINDCDC1 | DCDC1_EN = GND | 0.1 | 1 | μA | |||
rDS(on) | P-channel MOSFET on-resistance | VINDCDC1 = V(GS) = 3.6 V | 125 | 261 | mΩ | |||
Ilkg | P-channel leakage current | VINDCDC1 = 6 V | 2 | μA | ||||
rDS(on) | N-channel MOSFET on-resistance | VINDCDC1 = V(GS) = 3.6 V | 130 | 260 | mΩ | |||
Ilkg | N-channel leakage current | V(DS) = 6 V | 7 | 10 | μA | |||
Forward current limit (P- and N-channel) | 2.5 V < VI(MAIN) < 6 V | 1.55 | 1.75 | 1.95 | A | |||
fS | Oscillator frequency | 1.3 | 1.5 | 1.7 | MHz | |||
Fixed output voltage FPWMDCDC1 = 0 | 3 V | VINDCDC1 = 3.3 V to 6 V; 0 mA ≤ IO ≤ 1.2 A | –2% | 2% | ||||
3.3 V | VINDCDC1 = 3.6 V to 6 V; 0 mA ≤ IO ≤ 1.2 A | –2% | 2% | |||||
Fixed output voltage FPWMDCDC1 = 1 | 3 V | VINDCDC1 = 3.3 V to 6 V; 0 mA ≤ IO ≤ 1.2 A | –1% | 1% | ||||
3.3 V | VINDCDC1 = 3.6 V to 6 V; 0 mA ≤ IO ≤ 1.2 A | –1% | 1% | |||||
Adjustable output voltage with resistor divider at DEFDCDC1; FPWMDCDC1 = 0 | VINDCDC1 = VDCDC1 + 0.3 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1.2 A |
–2% | 2% | |||||
Adjustable output voltage with resistor divider at DEFDCDC1; FPWMDCDC1 = 1 | VINDCDC1 = VDCDC1 + 0.3 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1.2 A |
–1% | 1% | |||||
Line Regulation | VINDCDC1 = VDCDC1 + 0.3 V (min 2.5 V) to 6 V; IO = 10 mA |
0 | %/V | |||||
Load Regulation | IO = 10 mA to 1200 mA | 0.25 | %/A | |||||
Soft start ramp time | VDCDC1 ramping from 5% to 95% of target value | 750 | μs | |||||
Internal resistance from L1 to GND | 1 | MΩ | ||||||
VDCDC1 discharge resistance | DCDC1 discharge = 1 | 300 | Ω | |||||
VDCDC2 STEP-DOWN CONVERTER | ||||||||
VI | Input voltage range, VINDCDC2 | 2.5 | 6 | V | ||||
IO | Maximum output current | 1000 | mA | |||||
I(SD) | Shutdown supply current in VINDCDC2 | DCDC2_EN = GND | 0.1 | 1 | μA | |||
rDS(on) | P-channel MOSFET on-resistance | VINDCDC2 = V(GS) = 3.6 V | 140 | 300 | mΩ | |||
Ilkg | P-channel leakage current | VINDCDC2 = 6 V | 2 | μA | ||||
rDS(on) | N-channel MOSFET on-resistance | VINDCDC2 = V(GS) = 3.6 V | 150 | 297 | mΩ | |||
Ilkg | N-channel leakage current | V(DS) = 6 V | 7 | 10 | μA | |||
ILIMF | Forward current limit (P- and N-channel) | 2.5 V < VINDCDC2 < 6 V | 1.4 | 1.55 | 1.7 | A | ||
fS | Oscillator frequency | 1.3 | 1.5 | 1.7 | MHz | |||
Fixed output voltage FPWMDCDC2 = 0 | 1.8 V | VINDCDC2 = 2.5 V to 6 V; 0 mA ≤ IO ≤ 1 A | –2% | 2% | ||||
2.5 V | VINDCDC2 = 2.8 V to 6 V; 0 mA ≤ IO ≤ 1 A | –2% | 2% | |||||
Fixed output voltage FPWMDCDC2 = 1 | 1.8 V | VINDCDC2 = 2.5 V to 6 V; 0 mA ≤ IO ≤ 1 A | –2% | 2% | ||||
2.5 V | VINDCDC2 = 2.8 V to 6 V; 0 mA ≤ IO ≤ 1 A | –1% | 1% | |||||
Adjustable output voltage with resistor divider at DEFDCDC2 FPWMDCDC2 = 0 | VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1 A |
–2% | 2% | |||||
Adjustable output voltage with resistor divider at DEFDCDC2; FPWMDCDC2 = 1 | VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1 A |
–1% | 1% | |||||
Line Regulation | VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V) to 6 V; IO = 10 mA |
0 | %/V | |||||
Load Regulation | IO = 10 mA to 1 mA | 0.25 | %/A | |||||
Soft start ramp time | VDCDC2 ramping from 5% to 95% of target value | 750 | μs | |||||
Internal resistance from L2 to GND | 1 | MΩ | ||||||
VDCDC2 discharge resistance | DCDC2 discharge =1 | 300 | Ω | |||||
VDCDC3 STEP-DOWN CONVERTER | ||||||||
VI | Input voltage range, VINDCDC3 | 2.5 | 6 | V | ||||
IO | Maximum output current | 900 | mA | |||||
I(SD) | Shutdown supply current in VINDCDC3 | DCDC3_EN = GND | 0.1 | 1 | μA | |||
rDS(on) | P-channel MOSFET on-resistance | VINDCDC3 = V(GS) = 3.6 V | 310 | 698 | mΩ | |||
Ilkg | P-channel leakage current | VINDCDC3 = 6 V | 0.1 | 2 | μA | |||
rDS(on) | N-channel MOSFET on-resistance | VINDCDC3 = V(GS) = 3.6 V | 220 | 503 | mΩ | |||
Ilkg | N-channel leakage current | V(DS) = 6 V | 7 | 10 | μA | |||
Forward current limit (P- and N-channel) | 2.5 V < VINDCDC3 < 6 V | 1.15 | 1.34 | 1.52 | A | |||
fS | Oscillator frequency | 1.3 | 1.5 | 1.7 | MHz | |||
Fixed output voltage FPWMDCDC3 = 0 | All VDCDC3 | VINDCDC3 = 2.5 V to 6 V; 0 mA ≤ IO ≤ 800 mA | –2% | 2% | ||||
Fixed output voltage FPWMDCDC3 = 1 | All VDCDC3 | VINDCDC3 = 2.5 V to 6 V; 0 mA ≤ IO ≤ 800 mA | –1% | 1% | ||||
Adjustable output voltage with resistor divider at DEFDCDC3 FPWMDCDC3 = 0 | VINDCDC3 = VDCDC3 + 0.5 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 800 mA |
–2% | 2% | |||||
Adjustable output voltage with resistor divider at DEFDCDC3; FPWMDCDC3 = 1 | VINDCDC3 = VDCDC3 + 0.5 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 800 mA |
–1% | 1% | |||||
Line Regulation | VINDCDC3 = VDCDC3 + 0.3 V (min 2.5 V) to 6 V; IO = 10 mA |
0 | %/V | |||||
Load Regulation | IO = 10 mA to 400 mA | 0.25 | %/A | |||||
Soft start ramp time | VDCDC3 ramping from 5% to 95% of target value | 750 | μs | |||||
Internal resistance from L3 to GND | 1 | MΩ | ||||||
VDCDC3 discharge resistance | DCDC3 discharge =1 | 300 | Ω | |||||
VLDO1 and VLDO2 LOW DROPOUT REGULATORS | ||||||||
VI | Input voltage range for LDO1, 2 | 1.5 | 6.5 | V | ||||
VO | LDO1 output voltage range | 1 | 3.3 | V | ||||
VO | LDO2 output voltage range | 1 | 3.3 | V | ||||
IO | Maximum output current for LDO1, LDO2 | VI = 1.8 V, VO = 1.3 V | 200 | mA | ||||
VI = 1.5 V, VO = 1.3 V | 120 | |||||||
I(SC) | LDO1 and LDO2 short circuit current limit | V(LDO1) = GND, V(LDO2) = GND | 400 | mA | ||||
Minimum voltage drop at LDO1, LDO2 | IO = 50 mA, VINLDO = 1.8 V | 120 | mV | |||||
IO = 50 mA, VINLDO = 1.5 V | 65 | 150 | ||||||
IO = 200 mA, VINLDO = 1.8 V | 300 | |||||||
Output voltage accuracy for LDO1, LDO2 | IO = 10 mA | –2% | 1% | |||||
Line regulation for LDO1, LDO2 | VINLDO1,2 = VLDO1,2 + 0.5 V (min 2.5 V) to 6.5 V, IO = 10 mA |
–1% | 1% | |||||
Load regulation for LDO1, LDO2 | IO = 0 mA to 50 mA | –1% | 1% | |||||
Regulation time for LDO1, LDO2 | Load change from 10% to 90% | 10 | μs | |||||
ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3 | ||||||||
VIH | High level input voltage | 1.3 | VCC | V | ||||
VIL | Low level input voltage | 0 | 0.1 | V | ||||
Input bias current | 0.001 | 0.05 | μA | |||||
THERMAL SHUTDOWN | ||||||||
T(SD) | Thermal shutdown | Increasing junction temperature | 160 | °C | ||||
Thermal shutdown hysteresis | Decreasing junction temperature | 20 | °C | |||||
INTERNAL UNDERVOLTAGE LOCK OUT | ||||||||
UVLO | Internal UVLO | VCC falling | –2% | 2.35 | 2% | V | ||
V(UVLO_HYST) | Internal UVLO comparator hysteresis | 120 | mV | |||||
VOLTAGE DETECTOR COMPARATORS | ||||||||
Comparator threshold (PWRFAIL_SNS, LOWBAT_SNS) | Falling threshold | –1% | 1 | 1% | V | |||
Hysteresis | 40 | 50 | 60 | mV | ||||
Propagation delay | 25 mV overdrive | 10 | μs | |||||
POWER GOOD | ||||||||
V(PGOODF) | VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, decreasing | –12% | –10% | –8% | ||||
V(PGOODR) | VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, increasing | –7% | –5% | –3% |
MIN | MAX | UNIT | ||
---|---|---|---|---|
fMAX | Clock frequency | 400 | kHz | |
twH(HIGH) | Clock high time | 600 | ns | |
twL(LOW) | Clock low time | 1300 | ns | |
tR | DATA and CLK rise time | 300 | ns | |
tF | DATA and CLK fall time | 300 | ns | |
th(STA) | Hold time (repeated) START condition (after this period the first clock pulse is generated) | 600 | ns | |
th(DATA) | Setup time for repeated START condition | 600 | ns | |
th(DATA) | Data input hold time | 0 | ns | |
tsu(DATA) | Data input setup time | 100 | ns | |
tsu(STO) | STOP condition setup time | 600 | ns | |
t(BUF) | Bus free time | 1300 | ns |
FIGURE | ||
---|---|---|
Efficiency | vs Output current | Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10 |
Line transient response | Figure 11, Figure 12, Figure 13 | |
Load transient response | Figure 14, Figure 15, Figure 16 | |
Output voltage ripple | Figure 17, Figure 18, Figure 19 | |
Startup | Figure 20, Figure 21 | |
Line transient response | Figure 22, Figure 23, Figure 24 | |
Load transient response | Figure 25, Figure 26, Figure 27 |