JAJSF78L June   2006  – May 2018 TPS65023 , TPS65023B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3
    7. 7.7  Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
    8. 7.8  Electrical Characteristics: VDCDC1 Step-Down Converter
    9. 7.9  Electrical Characteristics: VDCDC2 Step-Down Converter
    10. 7.10 Electrical Characteristics: VDCDC3 Step-Down Converter
    11. 7.11 I2C Timing Requirements for TPS65023B
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VRTC Output and Operation With or Without Backup Battery
      2. 8.3.2  Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      3. 8.3.3  Power Save Mode Operation
      4. 8.3.4  Low Ripple Mode
      5. 8.3.5  Soft-Start
      6. 8.3.6  100% Duty Cycle Low Dropout Operation
      7. 8.3.7  Active Discharge When Disabled
      8. 8.3.8  Power-Good Monitoring
      9. 8.3.9  Low-Dropout Voltage Regulators
      10. 8.3.10 Undervoltage Lockout
      11. 8.3.11 Power-Up Sequencing
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 System Reset + Control Signals
        1. 8.5.1.1 DEFLDO1 and DEFLDO2
        2. 8.5.1.2 Interrupt Management and the INT Pin
      2. 8.5.2 Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1 VERSION Register Address: 00h (Read Only)
      2. 8.6.2 PGOODZ Register Address: 01h (Read Only)
      3. 8.6.3 MASK Register Address: 02h (Read and Write), Default Value: C0h
      4. 8.6.4 REG_CTRL Register Address: 03h (Read and Write), Default Value: FFh
      5. 8.6.5 CON_CTRL Register Address: 04h (Read and Write), Default Value: B1h
      6. 8.6.6 CON_CTRL2 Register Address: 05h (Read and Write), Default Value: 40h
      7. 8.6.7 DEFCORE Register Address: 06h (Read and Write), Default Value: 14h/1Eh
      8. 8.6.8 DEFSLEW Register Address: 07h (Read and Write), Default Value: 06h
      9. 8.6.9 LDO_CTRL Register Address: 08h (Read and Write), Default Value: Set with DEFLDO1 and DEFLDO2
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Voltage Connection
      2. 9.1.2 Unused Regulators
      3. 9.1.3 Reset Condition of DCDC1
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection for the DC-DC Converters
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Output Voltage Selection
        5. 9.2.2.5 VRTC Output
        6. 9.2.2.6 LDO1 and LDO2
        7. 9.2.2.7 TRESPWRON
        8. 9.2.2.8 VCC Filter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Requirements for Supply Voltages Below 3.0 V
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RSB|40
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
CONTROL SIGNALS: SCLK, SDAT (INPUT) FOR TPS65023
VIH High level input voltage (except the SDAT pin) Resistor pullup at SCLK = 4.7 kΩ, pulled to VRTC 1.3 VCC V
VIH High level input voltage for the SDAT pin Resistor pullup at SDAT = 4.7 kΩ, pulled to VRTC 1.45 VCC V
VIL Low level input voltage Resistor pullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC 0 0.4 V
IH Input bias current 0.01 0.1 μA
CONTROL SIGNALS: SCLK, SDAT (INPUT) FOR TPS65023B
VIH High level input voltage for the SCLK pin Rpullup at SCLK = 4.7 kΩ, pulled to VRTC;
For VCC = 2.5 V to 5.25 V		 1.4 VCC V
VIH High level input voltage for the SDAT pin Rpullup at SDAT = 4.7 kΩ, pulled to VRTC;
For VCC = 2.5 V to 5.25 V		 1.69 VCC V
VIH High level input voltage for the SDAT pin Rpullup at SDAT = 4.7 kΩ, pulled to VRTC;
For VCC = 2.5 V to 4.5 V		 1.55 VCC V
VIL Low level input voltage Rpullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC 0 0.35 V
IH Input bias current 0.01 0.1 μA
CONTROL SIGNALS: HOT_RESET, DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2
VIH High-level input voltage 1.3 VCC V
VIL Low-level input voltage 0 0.4 V
IIB Input bias current 0.01 0.1 μA
tdeglitch Deglitch time at HOT_RESET 25 30 35 ms
CONTROL SIGNALS: LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (OUTPUT)
VOH High-level output voltage 6 V
VOL Low-level output voltage IIL = 5 mA 0 0.3 V
Duration of low pulse at RESPWRON External capacitor 1 nF 100 ms
ICONST Internal charge / discharge current on pin TRESPWRON Used for generating RESPWRON delay 1.7 2 2.3 μA
TRESPWRON_LOWTH Internal lower comparator threshold on pin TRESPWRON Used for generating RESPWRON delay 0.225 0.25 0.275 V
TRESPWRON_UPTH Internal upper comparator threshold on pin TRESPWRON Used for generating RESPWRON delay 0.97 1 1.103 V
Resetpwron threshold VRTC falling –3% 2.4 3% V
Resetpwron threshold VRTC rising –3% 2.52 3% V
ILK Leakage current Output inactive high 0.1 μA
VLDO1 AND VLDO2 LOW DROPOUT REGULATORS
VI Input voltage range for LDO1, 2 1.5 6.5 V
VO(LD01) LDO1 output voltage range 1 3.15 V
VO(LDO2) LDO2 output voltage range 1 3.3 V
IO Maximum output current for LDO1, LDO2 VI = 1.8 V, VO = 1.3 V 200 mA
VI = 1.5 V, VO = 1.3 V 120
I(SC) LDO1 and LDO2 short-circuit current limit V(LDO1) = GND, V(LDO2) = GND 400 mA
Minimum voltage drop at LDO1, LDO2 IO = 50 mA, VINLDO = 1.8 V 120 mV
IO = 50 mA, VINLDO = 1.5 V 65 150
IO = 200 mA, VINLDO = 1.8 V 300
Output voltage accuracy for LDO1, LDO2 IO = 10 mA –2% 1%
Line regulation for LDO1, LDO2 VINLDO1, 2 = VLDO1,2 + 0.5 V
(min. 2.5 V) to 6.5 V, IO = 10 mA 		–1% 1%
Load regulation for LDO1, LDO2 IO = 0 mA to 50 mA –1% 1%
Regulation time for LDO1, LDO2 Load change from 10% to 90% 10 μs
ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3
VIH High-level input voltage 1.3 VCC V
VIL Low-level input voltage 0 0.1 V
Input bias current 0.001 0.05 μA
THERMAL SHUTDOWN
T(SD) Thermal shutdown Increasing junction temperature 160 °C
Thermal shutdown hysteresis Decreasing junction temperature 20 °C
INTERNAL UNDERVOLTAGE LOCK OUT
UVLO Internal UVLO VCC falling –2% 2.35 2% V
V(UVLO_HYST) Internal UVLO comparator hysteresis 120 mV
VOLTAGE DETECTOR COMPARATORS
Comparator threshold
(PWRFAIL_SNS, LOWBAT_SNS)		 Falling threshold –1% 1 1% V
Hysteresis 40 50 60 mV
Propagation delay 25-mV overdrive 10 μs
POWER-GOOD
V(PGOODF) VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, decreasing –12% –10% –8%
V(PGOODR) VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, increasing –7% –5% –3%
(1) Typical values are at TA = 25°C, unless otherwise noted.