JAJSF78L June   2006  – May 2018 TPS65023 , TPS65023B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3
    7. 7.7  Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
    8. 7.8  Electrical Characteristics: VDCDC1 Step-Down Converter
    9. 7.9  Electrical Characteristics: VDCDC2 Step-Down Converter
    10. 7.10 Electrical Characteristics: VDCDC3 Step-Down Converter
    11. 7.11 I2C Timing Requirements for TPS65023B
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VRTC Output and Operation With or Without Backup Battery
      2. 8.3.2  Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      3. 8.3.3  Power Save Mode Operation
      4. 8.3.4  Low Ripple Mode
      5. 8.3.5  Soft-Start
      6. 8.3.6  100% Duty Cycle Low Dropout Operation
      7. 8.3.7  Active Discharge When Disabled
      8. 8.3.8  Power-Good Monitoring
      9. 8.3.9  Low-Dropout Voltage Regulators
      10. 8.3.10 Undervoltage Lockout
      11. 8.3.11 Power-Up Sequencing
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 System Reset + Control Signals
        1. 8.5.1.1 DEFLDO1 and DEFLDO2
        2. 8.5.1.2 Interrupt Management and the INT Pin
      2. 8.5.2 Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1 VERSION Register Address: 00h (Read Only)
      2. 8.6.2 PGOODZ Register Address: 01h (Read Only)
      3. 8.6.3 MASK Register Address: 02h (Read and Write), Default Value: C0h
      4. 8.6.4 REG_CTRL Register Address: 03h (Read and Write), Default Value: FFh
      5. 8.6.5 CON_CTRL Register Address: 04h (Read and Write), Default Value: B1h
      6. 8.6.6 CON_CTRL2 Register Address: 05h (Read and Write), Default Value: 40h
      7. 8.6.7 DEFCORE Register Address: 06h (Read and Write), Default Value: 14h/1Eh
      8. 8.6.8 DEFSLEW Register Address: 07h (Read and Write), Default Value: 06h
      9. 8.6.9 LDO_CTRL Register Address: 08h (Read and Write), Default Value: Set with DEFLDO1 and DEFLDO2
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Voltage Connection
      2. 9.1.2 Unused Regulators
      3. 9.1.3 Reset Condition of DCDC1
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection for the DC-DC Converters
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Output Voltage Selection
        5. 9.2.2.5 VRTC Output
        6. 9.2.2.6 LDO1 and LDO2
        7. 9.2.2.7 TRESPWRON
        8. 9.2.2.8 VCC Filter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Requirements for Supply Voltages Below 3.0 V
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RSB|40
サーマルパッド・メカニカル・データ
発注情報

7.12 Typical Characteristics

Table 1. Table of Graphs

FIGURE
η Efficiency vs Output current Figure 5, Figure 6, Figure 7,
Figure 8, Figure 9, Figure 10
Output voltage vs Output current at 85°C Figure 11, Figure 12
Line transient response Figure 13, Figure 14, Figure 15
Load transient response Figure 16, Figure 17, Figure 18
VDCDC2 PFM operation Figure 19
VDCDC2 low ripple PFM operation Figure 20
VDCDC2 PWM operation Figure 21
Startup VDCDC1, VDCDC2 and VDCDC3 Figure 22
Startup LDO1 and LDO2 Figure 23
Line transient response Figure 24, Figure 25, Figure 26
Load transient response Figure 27, Figure 28, Figure 29
TPS65023 TPS65023B eff_5v_io1_lvs670.gifFigure 5. DCDC1: Efficiency vs Output Current
TPS65023 TPS65023B eff_18v_io1_lvs670.gifFigure 7. DCDC2: Efficiency vs Output Current
TPS65023 TPS65023B eff_18v_io3_lvs670.gifFigure 9. DCDC3: Efficiency vs Output Current
TPS65023 TPS65023B vo_io1_lvs670.gifFigure 11. DCDC2: Output Voltage
vs Output Current at 85°C
TPS65023 TPS65023B vindcdc1_lvs670.gif
Figure 13. VDCDC1 Line Transient Response
TPS65023 TPS65023B vindcdc3_lvs670.gifFigure 15. VDCDC3 Line Transient Response
TPS65023 TPS65023B vdcdc2_ld_lvs670.gifFigure 17. VDCDC2 Load Transient Response
TPS65023 TPS65023B vdcdc2_vo1_lvs670.gifFigure 19. VDCDC2 Output Voltage Ripple
TPS65023 TPS65023B vdcdc2_vo3_lvs670.gifFigure 21. VDCDC2 Output Voltage Ripple
TPS65023 TPS65023B startup_ldo_lvs607.gifFigure 23. Start-Up LDO1 and LDO2
TPS65023 TPS65023B ldo2_lt_lvs613.gifFigure 25. LDO2 Line Transient Response
TPS65023 TPS65023B ldo1_ld_lvs613.gifFigure 27. LDO1 Load Transient Response
TPS65023 TPS65023B vrtc_ld_lvs613.gifFigure 29. VRTC Load Transient Response
TPS65023 TPS65023B eff_5v_io2_lvs670.gifFigure 6. DCDC1: Efficiency vs Output Current
TPS65023 TPS65023B eff_18v_io2_lvs670.gifFigure 8. DCDC2: Efficiency vs Output Current
TPS65023 TPS65023B eff_18v_io4_lvs670.gifFigure 10. DCDC3: Efficiency vs Output Current
TPS65023 TPS65023B vo_io2_lvs670.gifFigure 12. DCDC3: Output Voltage
vs Output Current at 85°C
TPS65023 TPS65023B vindcdc2_lvs670.gifFigure 14. VDCDC2 Line Transient Response
TPS65023 TPS65023B vdcdc1_load_lvs670.gif
Figure 16. VDCDC1 Load Transient Response
TPS65023 TPS65023B vdcdc3_ld_lvs670.gifFigure 18. VDCDC3 Load Transient Response
TPS65023 TPS65023B vdcdc2_vo2_lvs670.gifFigure 20. VDCDC2 Output Voltage Ripple
TPS65023 TPS65023B startup_vdc_lvs670.gifFigure 22. Start-Up VDCDC1, VDCDC2, and VDCDC3
TPS65023 TPS65023B ldo1_lt_lvs613.gifFigure 24. LDO1 Line Transient Response
TPS65023 TPS65023B vrtc_lt_lvs613.gifFigure 26. VRTC Line Transient Response
TPS65023 TPS65023B ldo2_ld_lvs613.gifFigure 28. LDO2 Load Transient Response