JAJSF78L June   2006  – May 2018 TPS65023 , TPS65023B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3
    7. 7.7  Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
    8. 7.8  Electrical Characteristics: VDCDC1 Step-Down Converter
    9. 7.9  Electrical Characteristics: VDCDC2 Step-Down Converter
    10. 7.10 Electrical Characteristics: VDCDC3 Step-Down Converter
    11. 7.11 I2C Timing Requirements for TPS65023B
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VRTC Output and Operation With or Without Backup Battery
      2. 8.3.2  Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      3. 8.3.3  Power Save Mode Operation
      4. 8.3.4  Low Ripple Mode
      5. 8.3.5  Soft-Start
      6. 8.3.6  100% Duty Cycle Low Dropout Operation
      7. 8.3.7  Active Discharge When Disabled
      8. 8.3.8  Power-Good Monitoring
      9. 8.3.9  Low-Dropout Voltage Regulators
      10. 8.3.10 Undervoltage Lockout
      11. 8.3.11 Power-Up Sequencing
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 System Reset + Control Signals
        1. 8.5.1.1 DEFLDO1 and DEFLDO2
        2. 8.5.1.2 Interrupt Management and the INT Pin
      2. 8.5.2 Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1 VERSION Register Address: 00h (Read Only)
      2. 8.6.2 PGOODZ Register Address: 01h (Read Only)
      3. 8.6.3 MASK Register Address: 02h (Read and Write), Default Value: C0h
      4. 8.6.4 REG_CTRL Register Address: 03h (Read and Write), Default Value: FFh
      5. 8.6.5 CON_CTRL Register Address: 04h (Read and Write), Default Value: B1h
      6. 8.6.6 CON_CTRL2 Register Address: 05h (Read and Write), Default Value: 40h
      7. 8.6.7 DEFCORE Register Address: 06h (Read and Write), Default Value: 14h/1Eh
      8. 8.6.8 DEFSLEW Register Address: 07h (Read and Write), Default Value: 06h
      9. 8.6.9 LDO_CTRL Register Address: 08h (Read and Write), Default Value: Set with DEFLDO1 and DEFLDO2
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Voltage Connection
      2. 9.1.2 Unused Regulators
      3. 9.1.3 Reset Condition of DCDC1
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection for the DC-DC Converters
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Output Voltage Selection
        5. 9.2.2.5 VRTC Output
        6. 9.2.2.6 LDO1 and LDO2
        7. 9.2.2.7 TRESPWRON
        8. 9.2.2.8 VCC Filter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Requirements for Supply Voltages Below 3.0 V
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RSB|40
サーマルパッド・メカニカル・データ
発注情報

8.3.1 VRTC Output and Operation With or Without Backup Battery

The VRTC pin is an always-on output, intended to supply up to 30 mA to a permanently required rail (that is, for a real time clock). The TPS65023x asserts the RESPWRON signal if VRTC drops below 2.4 V. VRTC is selected from a priority scheme based on the VSYSIN and VBACKUP inputs.

When the voltage at the VSYSIN pin exceeds 2.65 V, VRTC connects to the VSYSIN input through a PMOS switch and all other paths to VRTC are disabled. The PMOS switch drops a maximum of 375 mV at 30 mA, which must be considered when using VRTC. VSYSIN can be connected to any voltage source with the appropriate input voltage, including VCC or, if set to 3.3-V output, DCDC2 or DCDC3. When VSYSIN falls below 2.65 V or shorts to ground, the PMOS switch connecting VRTC and VSYSIN opens and VRTC then connects to either VBACKUP or the output of a dedicated 3-V or 30-mA LDO.

NOTE

Texas Instruments recommends connecting VSYSIN to VCC or ground – VCC if a non-replaceable primary cell is connected to VBACKUP and ground if the VRTC output will float.

If the PMOS switch between VSYSIN and VRTC is open and VBACKUP exceeds 2.65 V, VRTC connects to VBACKUP through a PMOS switch. The PMOS switch drops a maximum of 375 mV at 30 mA, which must be considered if using VRTC. A typical application may connect VBACKUP to a primary Li button cell, but any battery that provides a voltage between 2.65 V and 6 V (that is, a single Li-Ion cell or a single boosted NiMH battery) is acceptable, to supply the VRTC output.

NOTE

In systems with no backup battery, the VBACKUP pin must be connected to GND.

If the switches between VRTC and VSYSIN or VBACKUP are open, the dedicated 3-V or 30-mA LDO, driven from VCC, connects to VRTC. This LDO is disabled if the voltage at the VSYSIN input exceeds 2.65 V.

Inside TPS65023x there is a switch (Vmax switch) which selects the higher voltage between VCC and VBACKUP. This is used as the supply voltage for some basic functions. The functions powered from the output of the Vmax switch are:

  • INT output
  • RESPWRON output
  • HOT_RESET input
  • LOW_BATT output
  • PWRFAIL output
  • Enable pins for DC-DC converters, LDO1 and LDO2
  • Undervoltage lockout comparator (UVLO)
  • Reference system with low frequency timing oscillators
  • LOW_BATT and PWRFAIL comparators

The main 2.25-MHz oscillator, and the I2C interface are only powered from VCC.

TPS65023 TPS65023B vrtc_sch_lvs607.gif
A. V_VSYSIN, V_VBACKUP thresholds: falling = 2.55 V, rising = 2.65 V ±3%
B. RESPWRON thresholds: falling = 2.4 V, rising = 2.52 V ±3%
Figure 30. RTC and nRESPWRON