JAJSF78L June   2006  – May 2018 TPS65023 , TPS65023B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3
    7. 7.7  Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
    8. 7.8  Electrical Characteristics: VDCDC1 Step-Down Converter
    9. 7.9  Electrical Characteristics: VDCDC2 Step-Down Converter
    10. 7.10 Electrical Characteristics: VDCDC3 Step-Down Converter
    11. 7.11 I2C Timing Requirements for TPS65023B
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VRTC Output and Operation With or Without Backup Battery
      2. 8.3.2  Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      3. 8.3.3  Power Save Mode Operation
      4. 8.3.4  Low Ripple Mode
      5. 8.3.5  Soft-Start
      6. 8.3.6  100% Duty Cycle Low Dropout Operation
      7. 8.3.7  Active Discharge When Disabled
      8. 8.3.8  Power-Good Monitoring
      9. 8.3.9  Low-Dropout Voltage Regulators
      10. 8.3.10 Undervoltage Lockout
      11. 8.3.11 Power-Up Sequencing
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 System Reset + Control Signals
        1. 8.5.1.1 DEFLDO1 and DEFLDO2
        2. 8.5.1.2 Interrupt Management and the INT Pin
      2. 8.5.2 Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1 VERSION Register Address: 00h (Read Only)
      2. 8.6.2 PGOODZ Register Address: 01h (Read Only)
      3. 8.6.3 MASK Register Address: 02h (Read and Write), Default Value: C0h
      4. 8.6.4 REG_CTRL Register Address: 03h (Read and Write), Default Value: FFh
      5. 8.6.5 CON_CTRL Register Address: 04h (Read and Write), Default Value: B1h
      6. 8.6.6 CON_CTRL2 Register Address: 05h (Read and Write), Default Value: 40h
      7. 8.6.7 DEFCORE Register Address: 06h (Read and Write), Default Value: 14h/1Eh
      8. 8.6.8 DEFSLEW Register Address: 07h (Read and Write), Default Value: 06h
      9. 8.6.9 LDO_CTRL Register Address: 08h (Read and Write), Default Value: Set with DEFLDO1 and DEFLDO2
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Voltage Connection
      2. 9.1.2 Unused Regulators
      3. 9.1.3 Reset Condition of DCDC1
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection for the DC-DC Converters
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Output Voltage Selection
        5. 9.2.2.5 VRTC Output
        6. 9.2.2.6 LDO1 and LDO2
        7. 9.2.2.7 TRESPWRON
        8. 9.2.2.8 VCC Filter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Requirements for Supply Voltages Below 3.0 V
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RSB|40
サーマルパッド・メカニカル・データ
発注情報

8.6.7 DEFCORE Register Address: 06h (Read and Write), Default Value: 14h/1Eh

Table 11. DEFCORE Register

DEFCORE B7 B6 B5 B4 B3 B2 B1 B0
Bit name and function – – – CORE4 CORE3 CORE2 CORE1 CORE0
Default 0 0 0 1 DEFDCDC1 DEFDCDC1 DEFDCDC1 DEFDCDC1
Default value loaded – – – RESET(1) RESET(1) RESET(1) RESET(1) RESET(1)
Read and write – – – R/W R/W R/W R/W R/W

RESET(1): DEFCORE is reset to its default value by one of these events:

  • undervoltage lockout (UVLO)
  • HOT_RESET pulled low
  • RESPWRON active
  • VRTC below threshold

Table 12. DCDC3 DVS Voltages

CORE4 CORE3 CORE2 CORE1 CORE0 VDCDC1   CORE4 CORE3 CORE2 CORE1 CORE0 VDCDC1
0 0 0 0 0 0.8 V   1 0 0 0 0 1.2 V
0 0 0 0 1 0.825 V 1 0 0 0 1 1.225 V
0 0 0 1 0 0.85 V 1 0 0 1 0 1.25 V
0 0 0 1 1 0.875 V 1 0 0 1 1 1.275 V
0 0 1 0 0 0.9 V 1 0 1 0 0 1.3 V
0 0 1 0 1 0.925 V 1 0 1 0 1 1.325 V
0 0 1 1 0 0.95 V 1 0 1 1 0 1.35 V
0 0 1 1 1 0.975 V 1 0 1 1 1 1.375 V
0 1 0 0 0 1 V 1 1 0 0 0 1.4 V
0 1 0 0 1 1.025 V 1 1 0 0 1 1.425 V
0 1 0 1 0 1.05 V 1 1 0 1 0 1.45 V
0 1 0 1 1 1.075 V 1 1 0 1 1 1.475 V
0 1 1 0 0 1.1 V 1 1 1 0 0 1.5 V
0 1 1 0 1 1.125 V 1 1 1 0 1 1.525 V
0 1 1 1 0 1.15 V 1 1 1 1 0 1.55 V
0 1 1 1 1 1.175 V 1 1 1 1 1 1.6 V