SLVS774C June   2007  – January 2016 TPS650240 , TPS650241 , TPS650242 , TPS650243 , TPS650244 , TPS650245

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Control Signals and Supply Pins
    6. 7.6  Electrical Characteristics: VDCDC1 Step-Down Converter
    7. 7.7  Electrical Characteristics: VDCDC2 Step-Down Converter
    8. 7.8  Electrical Characteristics: VDCDC3 Step-Down Converter
    9. 7.9  Electrical Characteristics: General
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Step-Down Converters, VDCDC1, VDCDC2 and VDCDC3
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Save Mode Operation
      2. 8.4.2 Soft-Start
      3. 8.4.3 100% Duty Cycle Low-Dropout Operation
      4. 8.4.4 Low-Dropout Voltage Regulators
      5. 8.4.5 Undervoltage Lockout
      6. 8.4.6 Power-Up Sequencing
      7. 8.4.7 PWRFAIL
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Voltage Selection
      2. 9.1.2 Voltage Change on VDCDC3
      3. 9.1.3 Vdd_alive Output
      4. 9.1.4 LDO1 and LDO2
      5. 9.1.5 VCC Filter
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Configuration for the Samsung Processor S3C6400-533MHz
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Inductor Selection for the DC-DC Converters
          2. 9.2.1.2.2 Output Capacitor Selection
          3. 9.2.1.2.3 Input Capacitor Selection
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Typical Configuration for the Titan 2 Processor
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RHB Package
32-Pin VQFN
Top View
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 po_lvs774.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
SWITCHING REGULATOR SECTION
AGND1 31 – Analog ground connection. All analog ground pins are connected internally on the chip.
AGND2 13 – Analog ground connection. All analog ground pins are connected internally on the chip.
9 I Input signal indicating default VDCDC1 voltage, 0 = 2.80 V, 1 = 3.3 V
DEFDCDC1 This pin can also be connected to a resistor divider between VDCDC1 and GND. In this case the output voltage of the DCDC1 converter can be set in a range from 0.6V to VINDCDC1
22 I Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 2.5 V
DEFDCDC2 This pin can also be connected to a resistor divider between VDCDC2 and GND. In this case the output voltage of the DCDC2 converter can be set in a range from 0.6V to VINDCDC2.
DEFDCDC3 32 I Input signal indicating VDCDC3 voltage.
TPS650240: 0 = 1.0 V, 1 = 1.3 V
TPS650241: 0 = 0.9 V, 1 = 1.375 V
TPS650242: 0 = 1.0 V, 1 = 1.5 V
TPS650243: 0 = 1.0 V, 1 = 1.2 V
TPS650244: 0 = 1.55 V, 1 = 1.6 V
TPS650245: 0 = 0.9 V, 1 = 1.1 V
EN_DCDC1 20 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.
EN_DCDC2 19 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.
EN_DCDC3 18 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.
L1 6 – Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.
L2 27 – Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.
L3 3 – Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.
PGND1 7 – Power ground for VDCDC1 converter
PGND2 26 – Power ground for VDCDC2 converter
PGND3 2 – Power ground for VDCDC3 converter
PowerPad – – Connect the power pad to analog ground
VCC 29 I Power supply for digital and analog circuitry of DCDC1, DCDC2, and DCDC3 DC-DC converters. This must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2.
VDCDC1 8 I VDCDC1 feedback voltage sense input, connect directly to VDCDC1
VDCDC2 25 I VDCDC2 feedback voltage sense input, connect directly to VDCDC2
VDCDC3 1 I VDCDC3 feedback voltage sense input, connect directly to VDCDC3
VINDCDC1 5 I Input voltage for VDCDC1 step-down converter. This must be connected to the same voltage supply as VINDCDC2, VINDCDC3, and VCC.
VINDCDC2 28 I Input voltage for VDCDC2 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC3, and VCC.
VINDCDC3 4 I Input voltage for VDCDC3 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC2, and VCC.
LDO REGULATOR SECTION
EN_LDO 17 I Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs.
EN_Vdd_alive 24 I Enable input for Vdd_alive LDO. Logic high enables the LDO, logic low disables the LDO.
FB_LDO1 11 I Feedback pin for LDO1
FB_LDO2 10 I Feedback pin for LDO2
Vdd_alive 12 O Output voltage for Vdd_alive
VINLDO 15 I Input voltage for LDO1 and LDO2
VLDO1 16 O Output voltage of LDO1
VLDO2 14 O Output voltage of LDO2
CONTROL AND I2C SECTION
MODE 23 I Select between power safe mode and forced PWM mode for DCDC1, DCDC2, and DCDC3. In power safe mode PFM is used at light loads, PWM for higher loads. If PIN is set to high level, forced PWM mode is selected. If the pin has low level, then the device operates in power safe mode.
PWRFAIL 21 O Open-drain output. Active low when PWRFAIL comparator indicates low VBAT condition.
PWRFAIL_SNS 30 I Input for the comparator driving the PWRFAIL output