SLVS774C June   2007  – January 2016 TPS650240 , TPS650241 , TPS650242 , TPS650243 , TPS650244 , TPS650245

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Control Signals and Supply Pins
    6. 7.6  Electrical Characteristics: VDCDC1 Step-Down Converter
    7. 7.7  Electrical Characteristics: VDCDC2 Step-Down Converter
    8. 7.8  Electrical Characteristics: VDCDC3 Step-Down Converter
    9. 7.9  Electrical Characteristics: General
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Step-Down Converters, VDCDC1, VDCDC2 and VDCDC3
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Save Mode Operation
      2. 8.4.2 Soft-Start
      3. 8.4.3 100% Duty Cycle Low-Dropout Operation
      4. 8.4.4 Low-Dropout Voltage Regulators
      5. 8.4.5 Undervoltage Lockout
      6. 8.4.6 Power-Up Sequencing
      7. 8.4.7 PWRFAIL
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Voltage Selection
      2. 9.1.2 Voltage Change on VDCDC3
      3. 9.1.3 Vdd_alive Output
      4. 9.1.4 LDO1 and LDO2
      5. 9.1.5 VCC Filter
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Configuration for the Samsung Processor S3C6400-533MHz
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Inductor Selection for the DC-DC Converters
          2. 9.2.1.2.2 Output Capacitor Selection
          3. 9.2.1.2.3 Input Capacitor Selection
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Typical Configuration for the Titan 2 Processor
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Input voltage range on all pins except A/PGND, VLDO1, and VLDO2 pins,
with respect to AGND		 –0.3 7 V
Voltage range on pins VLDO1 and VLDO2 with respect to AGND –0.3 3.6 V
Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3 2000 mA
Peak current at all other pins 1000 mA
TA Operating free-air temperature –40 85 °C
TJ Maximum junction temperature 125 °C
Lead temperature 1.6 mm (1/16-inch) from case for 10 seconds 260 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VINDCDC1, VINDCDC2, VINDCDC3, VCC Input voltage range step-down converters 2.5 6 V
VDCDC1 Output voltage range for VDCDC1 step-down converter(1) 0.6 VINDCDC1 V
VDCDC2 Output voltage range for mem step-down converter(1) 0.6 VINDCDC2 V
VDCDC3 Output voltage range for core step-down converter 0.9 1.5 V
VINLDO1, VINLDO2 Input voltage range for LDOs 1.5 6.5 V
VLDO1-2 Output voltage range for LDOs 1 3.3 V
IOUTDCDC1 Output current at L1 1600 mA
L1 Inductor at L1(2) 1.5 2.2 μH
CINDCDC1 Input capacitor at VINDCDC1 (2) 10 μF
COUTDCDC1 Output capacitor at VDCDC1 (2) 10 22 μF
IOUTDCDC2 Output current at L2 1600 mA
L2 Inductor at L2(2) 1.5 2.2 μH
CINDCDC2 Input capacitor at VINDCDC2 (2) 10 μF
COUTDCDC2 Output capacitor at VDCDC2 (2) 10 22 μF
IOUTDCDC3 Output current at L3 800 mA
L3 Inductor at L3(2) 1.5 2.2 μH
CINDCDC3 Input capacitor at VINDCDC3 (2) 10 μF
COUTDCDC3 Output capacitor at VDCDC3 (2) 10 22 μF
CVcc Input capacitor at VCC(2) 1 μF
Cin1-2 Input capacitor at VINLDO(2) 1 μF
COUT1-2 Output capacitor at VLDO1, VLDO2(2) 2.2 μF
ILDO1,2 Output current at VLDO1, VLDO2 200 mA
CVRTC Output capacitor at Vdd_alive(2) 2.2 μF
IVdd_alive Output current at Vdd_alive 30 mA
TA Operating ambient temperature –40 85 °C
TJ Operating junction temperature –40 125 °C
RCC Resistor from VINDCDC3,VINDCDC2, VINDCDC1 to VCC used for filtering(3) 1 10 Ω
(1) When using an external resistor divider at DEFDCDC2, DEFDCDC1.
(2) See Inductor Selection for the DC-DC Converters for more information, for Vout > 2.85 V choose 3.3-μH inductor.
(3) Up to 2.5-mA can flow into VCC when all 3 converters are running in PWM, this resistor causes the UVLO threshold to be shifted accordingly.

7.4 Thermal Information

THERMAL METRIC(1) TPS650240 UNIT
RHB (VQFN)
32 PINS
RθJA Junction-to-ambient thermal resistance 32.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 22.0 °C/W
RθJB Junction-to-board thermal resistance 6.2 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 6.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

7.5 Electrical Characteristics: Control Signals and Supply Pins

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, TA = –40°C to +85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
CONTROL SIGNALS: EN_DCDC1, EN_DCDC2, EN_DCDC3, EN_LDO, MODE, EN_VDD_ALIVE
VIH High level input voltage 1.45 VCC V
VIL Low level input voltage 0 0.4 V
IH Input bias current 0.01 0.1 μA
SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3
I(qPFM) Operating quiescent current VCC = 3.6 V PFM all 3 DCDC converters enabled, zero load
and no switching, LDOs enabled		 135 170 uA
PFM all 3 DCDC converters enabled, zero load
and no switching, LDO1, LDO2 = OFF,
Vdd_alive = ON		 75 100
PFM DCDC1 and DCDC2 converters enabled,
zero load and no switching,
LDO1, LDO2 = OFF, Vdd_alive = ON		 55 80
PFM DCDC1 converter enabled, zero load
and no switching, LDO1, LDO2 = OFF,
Vdd_alive = ON		 40 60
IVcc(PWM) Current into VCC; PWM VCC = 3.6 V All 3 DCDC converters enabled
and running in PWM, LDOs off 		2 mA
PWM DCDC1 and DCDC2 converters enabled
and running in PWM, LDOs off		 1.5 2.5
PWM DCDC1 converter enabled
and running in PWM, LDOs off		 0.85 2
Iq Quiescent current VCC = 3.6 V All converters disabled, LDO1, LDO2 = OFF,
Vdd_alive = OFF		 16 μA
All converters disabled, LDO1, LDO2 = OFF,
Vdd_alive = ON		 26
(1) Typical values are at TA = 25°C

7.6 Electrical Characteristics: VDCDC1 Step-Down Converter

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, TA = –40°C to +85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VVINDCDC1 Input voltage range 2.5 6 V
IO Maximum output current for TPS650240, TPS650242, and TPS650245 VO = 3.3 V 1000 mA
IO Maximum output current for TPS650241 and TPS650243 VO = 3.3 V 1600 mA
IO Maximum output current for TPS650244 VO = 3.3 V 800 mA
ISD Shutdown supply current in VINDCDC1 EN_DCDC1 = GND 0.1 1 μA
RDS(ON) P-channel MOSFET ON-resistance VINDCDC1 = VGS = 3.6 V 125 261 mΩ
ILP P-channel leakage current VINDCDC1 = 6 V 2 μA
RDS(ON) N-channel MOSFET ON-resistance VINDCDC1 = VGS = 3.6 V 130 260 mΩ
ILN N-channel leakage current VDS = 6.0 V 7 10 μA
ILIMF Forward current limit (P- and N-channel) for TPS650244 2.5 V < VINMAIN < 6.0 V 0.98 1.1 1.21 A
Forward current limit (P- and N-channel) for TPS650240, TPS650242, and TPS650245 2.5 V < VINMAIN < 6.0 V 1.15 1.3 1.39 A
Forward current limit (P- and N-channel) for TPS650241 and TPS650243 2.5 V < VINMAIN < 6.0 V 1.75 1.97 2.15 A
fS Oscillator frequency 1.95 2.25 2.55 MHz
VDCDC1 Fixed output voltage MODE = 0 (PWM/PFM) VINDCDC1 = 3.3 V to 6 V;
0 mA ≤ IO ≤ 1.6 A 		2.80 V –2% 2%
3.3 V –2% 2%
Fixed output voltage MODE = 1 (PWM) VINDCDC1 = 3.7 V to 6 V;
0 mA ≤ IO ≤ 1.6 A		 2.80 V –1% 1%
3.3 V –1% 1%
Adjustable output voltage with resistor divider at DEFDCDC1; MODE = 0 (PWM/PFM) VINDCDC1 = VDCDC1 +0.4 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1.6 A –2% 2%
Adjustable output voltage with resistor divider at DEFDCDC1; MODE = 1 (PWM) VINDCDC1 = VDCDC1 +0.4 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1.6 A –1% 1%
Line regulation VINDCDC1 = VDCDC1 + 0.3 V (min 2.5 V) to 6 V; IO = 10 mA 0% V
Load regulation IO = 10 mA to 1.6 A 0.25% A
TSS Soft-start ramp time VDCDC1 ramping from 5% to 95% of target value 750 μs
R(L1) Internal resistance from L1 to GND 1 MΩ
(1) Typical values are at TA = 25°C

7.7 Electrical Characteristics: VDCDC2 Step-Down Converter

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TA = –40°C to +85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VVINDCDC2 Input voltage range 2.5 6 V
IO Maximum output current for TPS650240, TPS650242, and TPS650245 VO = 2.5 V 800 mA
IO Maximum output current for TPS650241 and TPS650243 VO = 2.5 V 1000 mA
IO Maximum output current for TPS650244 VO = 2.5 V 1600 mA
ISD Shutdown supply current in VINDCDC2 EN_DCDC2 = GND 0.1 1 μA
RDS(ON) P-channel MOSFET ON-resistance VINDCDC2 = VGS = 3.6 V 140 300 mΩ
ILP P-channel leakage current VINDCDC2 = 6 V 2 μA
RDS(ON) N-channel MOSFET ON-resistance VINDCDC2 = VGS = 3.6 V 150 297 mΩ
ILN N-channel leakage current VDS = 6 V 7 10 μA
ILIMF Forward current limit (P- and N-channel) for TPS650240, TPS650242, and TPS650245 2.5 V < VINDCDC2 < 6 V 1.05 1.16 1.29 A
ILIMF Forward current limit (P- and N-channel) for TPS650241 and TPS650243 2.5 V < VINDCDC2 < 6 V 1.22 1.35 1.5 A
ILIMF Forward current limit (P- and N-channel) for TPS650244 2.5 V < VINDCDC2 < 6 V 1.75 1.97 2.15 A
fS Oscillator frequency 1.95 2.25 2.55 MHz
VDCDC2 Fixed output voltage MODE = 0 (PWM/PFM) VINDCDC2 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.6 A 		1.8 V –2% 2%
VINDCDC2 = 3.0 V to 6 V;
0 mA ≤ IO ≤ 1.6 A		 2.5 V –2% 2%
Fixed output voltage MODE = 1 (PWM) VINDCDC2 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.6 A 		1.8 V –2% 2%
VINDCDC2 = 3.0 V to 6 V;
0 mA ≤ IO ≤ 1.6 A		 2.5 V –1% 1%
Adjustable output voltage with resistor divider at DEFDCDC2; MODE = 0 (PWM) VINDCDC2 = VDCDC2 + 0.5 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1.6 A –2% 2%
Adjustable output voltage with resistor divider at DEFDCDC2; MODE = 1 (PWM) VINDCDC2 = VDCDC2 + 0.5 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1.6 A –1% 1%
Line regulation VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V) to 6 V; IO = 10 mA 0% V
Load regulation IO = 10 mA to 1.6 A 0.25% A
TSS Soft-start ramp time VDCDC2 ramping from 5% to 95% of target value 750 μs
R(L2) Internal resistance from L2 to GND 1 MΩ
(1) Typical values are at TA = 25°C

7.8 Electrical Characteristics: VDCDC3 Step-Down Converter

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TA = –40°C to +85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VVINDCDC3 Input voltage range 2.5 6 V
IO Maximum output current VO = 1.6 V 800 mA
ISD Shutdown supply current in VINDCDC3 EN_DCDC3 = GND 0.1 1 μA
RDS(ON) P-channel MOSFET ON-resistance VINDCDC3 = VGS = 3.6 V 310 698 mΩ
ILP P-channel leakage current VINDCDC3 = 6.0 V 0.1 2 μA
RDS(ON) N-channel MOSFET ON-resistance VINDCDC3 = VGS = 3.6 V 220 503 mΩ
ILN N-channel leakage current VDS = 6 V 7 10 μA
ILIMF Forward current limit (P- and N-channel) 2.5 V < VINDCDC3 < 6 V 1 1.2 1.4 A
fS Oscillator frequency 1.95 2.25 2.55 MHz
VDCDC3 Fixed output voltage MODE = 0 (PWM/PFM) VINDCDC3 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 800 mA, VO = 0.9 V to 1.6 V		 –2% 2%
Fixed output voltage MODE = 1 (PWM) –1% 1%
Line regulation VINDCDC3 = VDCDC3 + 0.3 V (min. 2.5 V) to 6 V;
IO = 10 mA 		0% V
Load regulation IO = 10 mA to 600 mA 0.25% A
TSS Soft-start ramp time VDCDC3 ramping from 5% to 95% of target value 750 μs
R(L3) Internal resistance from L3 to GND 1 MΩ
(1) Typical values are at TA = 25°C

7.9 Electrical Characteristics: General

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TA = –40°C to +85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT
VLDO1 AND VLDO2 LOW DROPOUT REGULATORS
I(q) Operating quiescent current Current per LDO into VINLDO 16 30 μA
I(SD) Shutdown current Total current into VINLDO, VLDO = 0 V 0.6 2 μA
VINLDO Input voltage range for LDO1, LDO2 1.5 6.5 V
VLDO1 LDO1 output voltage range 1 3.3 V
VLDO2 LDO2 output voltage range 1 3.3 V
VFB LDO1 and LDO2 feedback voltage See (1) 1 V
IO Maximum output current for LDO1, LDO2 Vin = 1.8 V, Vo = 1.3 V 200 mA
IO Maximum output current for LDO1, LDO2 Vin = 1.5 V; Vo = 1.3 V 120 mA
ISC LDO1 & LDO2 short circuit current limit VLDO1 = GND, VLDO2 = GND 400 mA
Minimum voltage drop at LDO1, LDO2 IO = 50 mA, VINLDO = 1.8 V 120 mV
Minimum voltage drop at LDO1, LDO2 IO = 50 mA, VINLDO = 1.5 V 65 150 mV
Minimum voltage drop at LDO1, LDO2 IO = 200 mA, VINLDO = 1.8 V 300 mV
Output voltage ccuracy for LDO1, LDO2 IO = 10 mA –2% 1%
Line regulation for LDO1, LDO2 VINLDO1,2 = VLDO1,2 + 0.5 V (min. 2.5 V) to 6.5 V, IO = 10 mA –1% 1%
Load regulation for LDO1, LDO2 IO = 0 mA to 200 mA –1% 1%
Regulation time for LDO1, LDO2 Load change from 10% to 90% 10 μs
Vdd_alive LOW DROPOUT REGULATOR
Vdd_alive Vdd_alive LDO output voltage,
TPS650240 to TPS650244		 IO = 0 mA 1.2 V
Vdd_alive LDO output voltage,
TPS650245		 IO = 0 mA 1.1
IO Output current for Vdd_alive 30 mA
ISC Vdd_alive short circuit current limit Vdd_alive = GND 100 mA
Output voltage accuracy for Vdd_alive IO = 0 mA –1% 1%
Line regulation for Vdd_alive VCC = Vdd_alive + 0.5 V to 6.5 V, IO = 0 mA –1% 1%
Regulation time for Vdd_alive Load change from 10% to 90% 10 μs
ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3
VIH High level input voltage 1.3 VCC V
VIL Low level input voltage 0 0.1 V
IH Input bias current 0.001 0.05 μA
THERMAL SHUTDOWN
TSD Thermal shutdown Increasing junction temperature 160 °C
Thermal shudown hysteresis Decreasing junction temperature 20 °C
INTERNAL UNDER VOLTAGE LOCK OUT
UVLO Internal UVLO VCC falling –3% 2.35 3% V
VUVLO_HYST Internal UVLO comparator hysteresis 120 mV
VOLTAGE DETECTOR COMPARATOR
PWRFAIL_SNS Comparator threshold Falling threshold –2% 1 2% V
Hysteresis 40 50 60 mV
Propagation delay 25 mV overdrive 10 μs
VOL Power fail output low voltage IOL = 5 mA 0.3 V
(1) If the feedback voltage is forced higher than above 1.2 V, a leakage current into the feedback pin may occur.
(2) Typical values are at TA = 25°C

7.10 Typical Characteristics

Table 1. Table of Graphs

FIGURE
η Efficiency VDCDC1 vs Load current PWM/PFM; VO = 3.3 V Figure 1
η Efficiency VDCDC1 vs Load current PWM; VO = 3.3 V Figure 2
η Efficiency VDCDC2 vs Load current PWM/PFM; VO = 1.8 V Figure 3
η Efficiency VDCDC2 vs Load current PWM; VO = 1.8 V Figure 4
η Efficiency VDCDC3 vs Load current PWM/PFM; VO = 1.3 V Figure 5
η Efficiency VDCDC3 vs Load current PWM; VO = 1.3 V Figure 6
Line transient response VDCDC1 Figure 7
Line transient response VDCDC2 Figure 8
Line transient response VDCDC3 Figure 9
Load transient response VDCDC1 Figure 10
Load transient response VDCDC2 Figure 11
Load transient response VDCDC3 Figure 12
Output voltage ripple DCDC2; PFM mode Figure 13
Output voltage ripple DCDC2; PWM mode Figure 14
Load regulation for Vdd_alive Figure 15
Start-up VDCDC1 to VDCDC3 Figure 16
Start-up LDO1 and LDO2 Figure 17
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 eff_io_lvs774.gif
Figure 1. DCDC1: Efficiency vs Output Current
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 eff_18v1_io_lvs774.gif
Figure 3. DCDC2: Efficiency vs Output Current
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 eff3_io_lvs774.gif
Figure 5. DCDC3: Efficiency vs Output Current
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 lin_trn_res_lvs774.gif
Figure 7. VDCDC1 Line Transient Response
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 lin2_trn_res_lvs774.gif
Figure 9. VDCDC3 Line Transient Response
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 ld_trn_res_lvs774.gif
Figure 11. VDCDC2 Load Transient Response
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 vdcdc2_vo1_lvs774.gif
Figure 13. VDCDC2 Output Voltage Ripple, PFM Mode
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 vo_io_lvs774.gif
Figure 15. VDD_ALIVE Output Voltage vs Output Current
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 ldo_startup_lvs774.gif
Figure 17. Start-Up LDO1 AND LDO2
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 eff2_io_lvs774.gif
Figure 2. DCDC1: Efficiency vs Output Current
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 eff_18v2_io_lvs774.gif
Figure 4. DCDC2: Efficiency vs Output Current
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 eff4_io_lvs774.gif
Figure 6. DCDC3: Efficiency vs Output Current
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 vdcdc2_lt_lvs774.gif
Figure 8. VDCDC2 Line Transient Response
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 ld3_trn_lvs774.gif
Figure 10. VDCDC1 Load Transient Response
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 ld2_trn_res_lvs774.gif
Figure 12. VDCDC3 Load Transient Response
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 vdcdc2_vo3_lvs774.gif
Figure 14. VDCDC2 Output Voltage Ripple, PWM Mode
TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 startup2_lvs774.gif
Figure 16. Startup VDCDC1, VDCDC2, VDCDC3