8.3.1 Operation of DCDC Converters

The TPS6505x devices include each two synchronous step-down converters. The converters operate with 2.25-MHz (typical) fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the converters automatically enter Power Save Mode and operate with PFM (Pulse Frequency Modulation).

During PWM operation the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on, and the inductor current ramps up until the current comparator trips, and the control logic turns off the switch. The current limit comparator turns off the switch if the current limit of the P-channel switch is exceeded. After the adaptive dead time, which prevents shoot through current, the N-channel MOSFET rectifier is turned on, and the inductor current ramps down. The next cycle is initiated by the clock signal turning off the N-channel rectifier, and turning on the on the P-channel switch.

The two DC-DC converters operate synchronized to each other, with converter 1 as the master. A 180° phase shift between converter 1 and converter 2 decreases the input RMS current. Therefore, smaller input capacitors can be used.

8.3.2 Power-Save Mode

The Power-Save Mode is enabled with the Mode pin set to 0. If the load current decreases, the converters enters Power-Save Mode operation automatically. During Power-Save Mode, the converters operate with reduced switching frequency in PFM mode, and with a minimum quiescent current to maintain high-efficiency. The converter positions the output voltage 1% above the nominal output voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step.

To optimize the converter efficiency at light load, the average current is monitored. If in PWM mode, the inductor current remains below a certain threshold, then Power-Save Mode is entered. The typical threshold is calculated according to Equation 1.

Equation 1.

A. Average output current threshold to enter PFM mode.

Equation 2.

A. Average output current threshold to leave PFM mode.

During the Power-Save Mode, the output voltage is monitored with a comparator. As the output voltage falls below the skip comparator threshold (skip comp), the P-channel switch turns on, and the converter effectively delivers a constant current. If the load is below the delivered current, the output voltage rises until the skip comp threshold is crossed again, then all switching activity ceases, reducing the quiescent current to a minimum until the output voltage has dropped below the threshold. If the load current is greater than the delivered current, the output voltage falls until it crosses the skip comparator low (Skip Comp Low) threshold set to 1% below nominal V_O, then Power-Save Mode is exited, and the converter returns to PWM mode

These control methods reduce the quiescent current to 12 μA per converter, and the switching frequency to a minimum, achieving the highest converter efficiency. The PFM mode operates with low output voltage ripple. The ripple depends on the comparator delay, and the size of the output capacitor; increasing capacitor values decreases the output ripple voltage.

The Power-Save Mode can be disabled by driving the MODE pin high. In forced PWM mode, both converters operate with fixed frequency PWM mode regardless of the load.

8.3.3 Dynamic Voltage Positioning

This feature reduces the voltage undershoots and overshoots at load steps from light to heavy load and vice versa. It is activated in Power-Save Mode operation when the converter runs in PFM Mode. It provides more headroom for both, the voltage drop at a load step and the voltage increase at a load throw-off. This improves load transient behavior.

At light loads, in which the converter operate in PFM Mode, the output voltage is regulated typically 1% greater than the nominal value. In the event of a load transient from light load to heavy load, the output voltage drops until it reaches the skip comparator low threshold set to –1% below the nominal value and enters PWM mode. During a release from heavy load to light load, the voltage overshoot is also minimized due to active regulation turning on the N-channel switch.

Figure 11. Dynamic Voltage Positioning

8.3.4 Soft Start

The two converters have an internal soft start circuit that limits the inrush current during start-up. During soft start, the output voltage ramp up is controlled as shown in Figure 12.

Figure 12. Soft Start

8.3.5 100% Duty Cycle Low Dropout Operation

The converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range (that is, the minimum input voltage to maintain regulation depends on the load current and output voltage) and can be calculated using Equation 3.

Equation 3.

where

• I_O max = maximum output current plus inductor ripple current.
• r_DS(on) max = maximum P-channel switch r_DS(on).
• R_L = DC resistance of the inductor.
• V_O (max) = nominal output voltage plus maximum output voltage tolerance.

8.3.6 Undervoltage Lockout

The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery and disables all internal circuitry. The undervoltage lockout threshold, which is sensed at the V_CC pin, is typically 1.8 V, 2 V (maximum).

8.3.7 Mode Selection

The MODE pin allows mode selection between forced PWM Mode and Power-Safe Mode for both converters. Connecting this pin to GND enables the automatic PWM and power save mode operation. The converters operates in fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, maintaining high-efficiency over a wide load current range.

Pulling the MODE pin high forces both converters to operate constantly in the PWM mode even at light load currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the Power-Save Mode during light loads. For additional flexibility, it is possible to switch from Power-Save Mode to forced PWM mode during operation. This allows efficient power management by adjusting the operation of the converter to the specific system requirements.

8.3.8 Enable

To start up each converter independently, the device has a separate enable pin for each DC-DC converter and for each LDO. If EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4 are set to high, the corresponding converter starts up with soft start as previously described.

Pulling the enable pin low forces the device into shutdown, with a shutdown quiescent current as defined in Electrical Characteristics. In this mode, the P and N-Channel MOSFETs are turned off, the and the entire internal control circuitry is switched off. If disabled, the outputs of the LDOs are pulled low by internal 350-Ω resistors, actively discharging the output capacitor. For proper operation, the enable pins must be terminated and must not be left unconnected.

8.3.9 RESET

The TPS65051, TPS65052, TPS65054, and TPS65056 devices contain circuitry that can generate a reset pulse for a processor with a 100-ms delay time. The input voltage at a comparator is sensed at an input called threshold. When the voltage exceeds the threshold, the output goes high with a 100-ms delay time. A hysteresis can be defined with an external resistor connected to the hysteresis input. This circuitry is functional as soon as the supply voltage at V_CC exceeds the undervoltage lockout threshold. Therefore, the TPS6505x devices have a shutdown current (all DC-DC converters and LDOs are off) of 9 μA to supply bandgap and comparator.

Figure 13. RESET Pulse Circuit

8.3.10 Push-Button ON-OFF (PB-ON-OFF)

The TPS65050 device provides a PB-ON-OFF functionality instead of supervising a voltage with the threshold and hysteresis inputs. The output at PB_OUT is held low after voltage is applied at V_CC. Only after the input at PB-IN is pulled high once, the output driver at PB_OUT goes to its inactive state, driven high with its external pullup resistor. Further low-high pulses at PB-IN toggles the status of the PB_OUT output, and can be used to shut down and start the converter with a single push on a button by connecting the PB_OUT output to the enable input of the converters.

Figure 14. Push-Button Circuit

8.3.11 Short-Circuit Protection

All outputs are short-circuit protected with a maximum output current as defined in the Electrical Characteristics.

8.3.12 Thermal Shutdown

As soon as the junction temperature, T_J, exceeds 150°C (typically) for the DC-DC converters, the device goes into thermal shutdown. In this mode, the P and N-Channel MOSFETs are turned off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis again. A thermal shutdown for one of the DC-DC converters disables both converters simultaneously.

The thermal shutdown temperature for the LDOs are set to typically 140°C. Therefore, a LDO, which may be used to power an external voltage, never heats up the chip high enough to turn off the DC-DC converters. If one LDO exceeds the thermal shutdown temperature, all LDOs turns off simultaneously.

8.3.13 Low Dropout Voltage Regulators

The low dropout voltage regulators are designed to operate well with small ceramic input and output capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 400 mV (LDO1) and 280 mV (LDO2, LDO3, and LDO4) at rated output current. Each LDO supports a current limit feature. The LDOs are enabled by the EN_LDO1, ENLDO2, EN_LDO3 and EN_LDO4 pin. In the TPS65050 and TPS65052 devices, the output voltage of the LDOs is set using 4 pins. The DEFLDO1 to DEFLDO4 pins can either be connected to GND or Vbat (V_CC) to define a set of output voltages for LDO1 to LDO4 according to table 1. Connecting the DEFLDOx pins to a voltage different from GND or V_CC causes increased leakage current into V_CC. In the TPS65051 and TPS65054 devices, the output voltage of the LDOs is set using external resistor dividers.

According to Table 1, The TPS65050 and TPS65052 devices default voltage options adjustable with DEFLDO4…DEFLDO1.