SLVS710C January   2007  – February 2017 TPS65050

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Operation of DCDC Converters
        1. 8.3.1.1 DCDC1 Converter
        2. 8.3.1.2 DCDC2 Converter
      2. 8.3.2  Power-Save Mode
      3. 8.3.3  Dynamic Voltage Positioning
      4. 8.3.4  Soft Start
      5. 8.3.5  100% Duty Cycle Low Dropout Operation
      6. 8.3.6  Undervoltage Lockout
      7. 8.3.7  Mode Selection
      8. 8.3.8  Enable
      9. 8.3.9  RESET
      10. 8.3.10 Push-Button ON-OFF (PB-ON-OFF)
      11. 8.3.11 Short-Circuit Protection
      12. 8.3.12 Thermal Shutdown
      13. 8.3.13 Low Dropout Voltage Regulators
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Setting
          1. 9.2.2.1.1 Converter 1 (DCDC1)
          2. 9.2.2.1.2 Converter 2 (DCDC2)
        2. 9.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Output Capacitor Selection
          3. 9.2.2.2.3 Input Capacitor Selection
        3. 9.2.2.3 Low Drop Out Voltage Regulators (LDOs)
        4. 9.2.2.4 PB-ONOFF and Sequencing
        5. 9.2.2.5 RESET
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resource
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

  • The input capacitors for the DC-DC converters should be placed as close as possible to the VINDCDC1/2 pin and the PGND1 and PGND2 pins.
  • The inductor of the output filter should be placed as close as possible to the device to provide the shortest switch node possible, reducing the noise emitted into the system and increasing the efficiency.
  • Sense the feedback voltage from the output at the output capacitors to ensure the best DC accuracy. Feedback should be routed away from noisy sources such as the inductor. If possible route on the opposing side as the switch node and inductor and place a GND plane between the feedback and the noisy sources or keepout underneath them entirely.
  • Place the output capacitors as close as possible to the inductor to reduce the feedback loop as much as possible. This will ensure best regulation at the feedback point.
  • Place the device as close as possible to the most demanding or sensitive load. The output capacitors should be placed close to the input of the load. This will ensure the best AC performance possible.
  • The input and output capacitors for the LDOs should be placed close to the device for best regulation performance.
  • TI recommends using the common ground plane for the layout of this device. The AGND can be separated from the PGND but, a large low parasitic PGND is required to connect the PGNDx pins to the CIN and external PGND connections. If the AGND and PGND planes are separated, have one connection point to reference the grounds together. Place this connection point close to the IC.

11.2 Layout Example

TPS65050 TPS65051 TPS65052 TPS65054 TPS65056 Layout.gif Figure 32. Layout Example from EVM for TPS6505x