SLVS710C January   2007  – February 2017 TPS65050

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Operation of DCDC Converters
        1. 8.3.1.1 DCDC1 Converter
        2. 8.3.1.2 DCDC2 Converter
      2. 8.3.2  Power-Save Mode
      3. 8.3.3  Dynamic Voltage Positioning
      4. 8.3.4  Soft Start
      5. 8.3.5  100% Duty Cycle Low Dropout Operation
      6. 8.3.6  Undervoltage Lockout
      7. 8.3.7  Mode Selection
      8. 8.3.8  Enable
      9. 8.3.9  RESET
      10. 8.3.10 Push-Button ON-OFF (PB-ON-OFF)
      11. 8.3.11 Short-Circuit Protection
      12. 8.3.12 Thermal Shutdown
      13. 8.3.13 Low Dropout Voltage Regulators
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Setting
          1. 9.2.2.1.1 Converter 1 (DCDC1)
          2. 9.2.2.1.2 Converter 2 (DCDC2)
        2. 9.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Output Capacitor Selection
          3. 9.2.2.2.3 Input Capacitor Selection
        3. 9.2.2.3 Low Drop Out Voltage Regulators (LDOs)
        4. 9.2.2.4 PB-ONOFF and Sequencing
        5. 9.2.2.5 RESET
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resource
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VI Input voltage range on all pins except AGND, PGND, and EN_LDO1 pins with respect to AGND –0.3 7 V
Input voltage range on EN_LDO1 pins with respect to AGND –0.3 VCC + 0.5 V
II Current at VINDCDC1/2, L1, PGND1, L2, PGND2 1800 mA
Current at all other pins 1000 mA
VO Output voltage range for LDO1, LDO2, LDO3, and LDO4 –0.3 4 V
Continuous total power dissipation See Dissipation Ratings
TA Operating free-air temperature –40 85 °C
TJ Maximum junction temperature 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VI Input voltage range for step-down converters, VINDCDC1/2 2.5 6 V
VO Output voltage range for step-down converter, VDCDC1 0.6 VINDCDC1/2 V
Output voltage range for step-down converter, VDCDC2 0.6 VINDCDC1/2 V
VI Input voltage range for LDOs, VINLDO1, VINLDO2, VINLDO3/4 1.5 6.5 V
VO Output voltage range for LDO1, LDO2, LDO3 and LDO4 1 3.6 V
IO Output current at L1 (DCDC1) for TPS65051, TPS65052 1000 mA
Output current at L1 (DCDC1) for TPS65050, TPS65054 600 mA
Output current at L1 (DCDC2) 600 mA
Output current at VLDO1, VLDO2 400 mA
Output current at VLDO3, VLDO4 200 mA
Inductor at L1, L2(1) 1.5 2.2 μH
CO Output capacitor at VDCDC1, VDCDC2(1) 10 22 μF
Output capacitor at VLDO1, VLDO2, VLDO3, VLDO4(1) 2.2 μF
CI Input capacitor at VCC(1) 1 μF
Input capacitor at VINLDO1/2/3/4(1) 2.2 μF
TA Operating ambient temperature range –40 85 °C
TJ Operating junction temperature range –40 125 °C
Rfilter Resistor from battery voltage to VCC used for filtering(2) 1 10 Ω
(1) See the Application and Implementation section of this data sheet for more details.
(2) Up to 2 mA can flow into VCC when both converters are running in PWM, this resistor causes the UVLO threshold to be shifted accordingly.

7.4 Thermal Information

THERMAL METRIC(1) TPS6505x UNIT
RSM (VQFN)
32 PINS
RθJA Junction-to-ambient thermal resistance 37.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 30.4 °C/W
RθJB Junction-to-board thermal resistance 8 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 7.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 μH, CO = 10 μF. TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VI Input voltage range at VINDCDC1/2 2.5 6 V
IQ Operating quiescent current
Total current into VCC, VINDCDC1/2, VINLDO1, VINLDO2, VINLDO3/4		 One converter, IO = 0 mA.
PFM mode enabled (Mode = GND) device not switching, EN_DCDC1 = VI OR EN_DCDC2 = VI; EN_LDO1= EN_LDO2 = EN_LDO3/4 = GND		 20 30 μA
Two converters, IO = 0 mA
PFM mode enabled (Mode = 0) device not switching, EN_DCDC1 = VI AND EN_DCDC2 = VI; EN_LDO1 = EN_LDO2 = EN_LDO3/4 = GND		 32 40 μA
One converter, IO = 0 mA.
PFM mode enabled (Mode = GND) device not switching, EN_DCDC1 = VI OR EN_DCDC2 = VI; EN_LDO1 = EN_LDO2 = EN_LDO3 = EN_LDO4 = VI 		180 250 μA
IQ Operating quiescent current into VCC One converter, IO = 0 mA.
Switching with no load (Mode = VI), PWM operation EN_DCDC1 = VI OR EN_DCDC2 = VI; EN_LDO1 = EN_LDO2 = EN_LDO3/4 = GND		 0.85 mA
Two converters, IO = 0 mA
Switching with no load (Mode = VI), PWM operation EN_DCDC1 = VI AND EN_DCDC2 = VI; EN_LDO1 = EN_LDO2 = EN_LDO3/4 = GND		 1.25 mA
I(SD) Shutdown current EN_DCDC1 = EN_DCDC2 = GND EN_LDO1 = EN_LDO2 = EN_LDO3 = EN_LDO4 = GND 9 12 μA
V(UVLO) Undervoltage lockout threshold for DCDC converters and LDOs Voltage at VCC 1.8 2 V
EN_DCDC1, EN_DCDC2, DEFDCDC2, DEFLDO1, DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4
VIH High-level input voltage MODE/DATA, EN_DCDC1, EN_DCDC2, DEFDCDC2, DEFLDO1, DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4 1.2 VCC V
VIL Low-level input voltage MODE/DATA, EN_DCDC1, EN_DCDC2, DEFLDO1, DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4, DEFDCDC2 0 0.4 V
IlB Input bias current MODE/DATA = GND or VI
MODE/DATA, EN_DCDC1, EN_DCDC2, DEFDCDC2, DEFLDO1, DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4		 0.01 1 μA
TPS65051 and TPS65052 only
V_FB_LDOx = 1 V
FB_LDO1, FB_LDO2, FB_LDO3, FB_LDO4		 100 nA
POWER SWITCH
rDS(on) P-channel MOSFET on resistance DCDC1 VINDCDC1/2 = 3.6 V 280 630 mΩ
VINDCDC1/2 = 2.5 V 400
DCDC2 VINDCDC1/2 = 3.6 V 280 630
VINDCDC1/2 = 2.5 V 400
Ilkg P-channel leakage current VDCDCx = V(DS) = 6 V 1 μA
rDS(on) N-channel MOSFET on resistance DCDC1 VINDCDC1/2 = 3.6 V 220 450 mΩ
VINDCDC1/2 = 2.5 V 320
DCDC2 VINDCDC1/2 = 3.6 V 220 450
VINDCDC1/2 = 2.5 V 320
Ilkg N-channel leakage current VDCDCx = V(DS) = 6 V 7 10 μA
I(LIMF) Forward current limit PMOS (High-Side) and NMOS (Low side) DCDC1: TPS65050
TPS65054		 2.5 V ≤ VINDCDC1/2 ≤ 6 V 0.85 1 1.15 A
TPS65051, TPS65052,
TPS65056		 1.19 1.4 1.65
DCDC2:
TPS65050 - TPS65056
 2.5 V ≤ VINDCDC1/2 ≤ 6 V 0.85 1 1.15 A
Thermal shutdown Increasing junction temperature 150 °C
Thermal shutdown hysteresis Decreasing junction temperature 20 °C
OSCILLATOR
fSW Oscillator frequency 2.025 2.25 2.475 MHz
OUTPUT
VO Output voltage range for DCDC1, DCDC2 externally adjustable versions 0.6 VINDCDC1/2 V
Output voltage for DCDC1 TPS65052 and TPS65056 3.3 V
Output voltage for DCDC2 TPS65052, TPS65054 and TPS65056 set by DEFDCDC2, see Table 3
Vref Reference voltage externally adjustable versions 600 mV
VO DC output voltage accuracy DCDC1, DCDC2(1) VINDCDC1/2 = 2.5 V to 6 V
0 mA < IO = < IO(max)
Mode = GND, PFM operation		 –2% 0 2%
VINDCDC1/2 = 2.5 V to 6 V
0 mA < IO = < IO(max)
Mode = VI, PWM operation		 –1% 0 1%
ΔVO Power save mode ripple voltage(2) IO = 1 mA, Mode = GND, VO = 1.3 V,
Bandwith = 20 MHz		 25 mVPP
tStart Start-up time time from active EN to Start switching 170 μs
tRamp VOUT Ramp up Time time to ramp from 5% to 95% of VO 750 μs
tRESET_DELAY RESET delay time Input voltage at threshold pin rising 80 100 120 ms
tPB_DB PB-ONOFF debounce time 26 32 38 ms
VOL RESET, PB_OUT output low voltage IOL = 1 mA, Vhysteresis < 1 V, Vthreshold < 1 V 0.2 V
IOL RESET, PB_OUT sink current 1 mA
Ileak RESET, PB_OUT output leakage current After PB_IN has been pulled high once; Vthreshold > 1 V and Vhysteresis > 1 V, VOH = 6 V 10 nA
Vth Vthreshold, Vhysteresis threshold 0.98 1 1.02 V
VLDO1, VLDO2, VLDO3 and VLDO4 Low Dropout Regulators
VI Input voltage range for LDO1, LDO2, LDO3, LDO4 1.5 6.5 V
VO LDO1 output voltage range TPS65050, TPS65052 only 1.2 3.3 V
LDO2 output voltage range TPS65050, TPS65052 only 1.8 3.3
LDO3 output voltage range TPS65050, TPS65052 only 1.1 3.3
LDO4 output voltage range TPS65050, TPS65052 only 1.2 2.85
V(FB) Feedback voltage for FB_LDO1, FB_LDO2, FB_LDO3, and FB_LDO4 TPS65051, TPS65054 and TPS65056 only 1 V
IO Maximum output current for LDO1, LDO2 400 mA
Maximum output current for LDO3, LDO4 200 mA
I(SC) LDO1 short-circuit current limit VLDO1 = GND 750 mA
LDO2 short-circuit current limit VLDO2 = GND 850 mA
LDO3 and LDO4 short-circuit current limit VLDO3 = GND, VLDO4 = GND 420 mA
Dropout voltage at LDO1 IO = 400 mA, VINLDO = 3.4 V 400 mV
Dropout voltage at LDO2 IO = 400 mA, VINLDO = 1.8 V 280 mV
Dropout voltage at LDO3, LDO4 IO = 200 mA, VINLDO = 1.8 V 280 mV
Ilkg Leakage current from VinLDOx to VLDOx LDO enabled, VINLDO = 6.5 V, VO = 1 V,
at TA = 140°C		 3 μA
VO Output voltage accuracy for LDO1, LDO2, LDO3, LDO4 IO = 10 mA –2% 1%
Line regulation for LDO1, LDO2, LDO3, LDO4 VINLDO1,2 = VLDO1,2 + 0.5 V (min. 2.5 V) to 6.5V, VINLDO3,4 = VLDO3,4 + 0.5 V (minimum 2.5 V) to 6.5 V,
IO = 10 mA		 –1% 1%
Load regulation for LDO1, LDO2, LDO3, LDO4 IO = 0 mA to 400 mA for LDO1, LDO2
IO = 0 mA to 200 mA for LDO3, LDO4		 –1% 1%
Regulation time for LDO1, LDO2, LDO3, LDO4 Load change from 10% to 90% 10 μs
PSRR Power supply rejection ratio f = 10 kHz; IO = 50 mA; VI = VO + 1 V 70 dB
R(DIS) Internal discharge resistor at VLDO1, VLDO2, VLDO3, VLDO4 active when LDO is disabled 350 R
Thermal shutdown Increasing junction temperature 140 °C
Thermal shutdown hysteresis Decreasing junction temperature 20 °C
(1) Output voltage specification does not include tolerance of external voltage programming resistors.
(2) In Power Save Mode, operation is typically entered at IPSM = VI / 32 Ω.

7.6 Dissipation Ratings

PACKAGE RθJA (1) POWER RATING
TA  ≤ 25°C		 DERATING FACTOR
ABOVE TA = 25°C		 POWER RATING
TA  = 70°C		 POWER RATING
TA  = 85°C
RSM 58 K/W 1.7 W 17 mW/K 0.95 W 0.68 W
(1) The thermal resistance junction to case of the RSM package is 4 K/W measured on a high K board

7.7 Typical Characteristics

TPS65050 TPS65051 TPS65052 TPS65054 TPS65056 eff1_v_vo_lvs710.gif Figure 1. Efficiency vs Output Current
TPS65050 TPS65051 TPS65052 TPS65054 TPS65056 eff3_v_vo_lvs710.gif Figure 3. Efficiency vs Output Current
TPS65050 TPS65051 TPS65052 TPS65054 TPS65056 pssr_v_f_lvs710.gif Figure 5. Power Supply Rejection Ratio vs Frequency
TPS65050 TPS65051 TPS65052 TPS65054 TPS65056 eff2_v_vo_lvs710.gif Figure 2. Efficiency vs Output Current
TPS65050 TPS65051 TPS65052 TPS65054 TPS65056 eff4_v_vo_lvs710.gif Figure 4. Efficiency vs Output Current