SWCS128A March   2015  – December 2015

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Total Current Consumption
    6. 4.6  Electrical Characteristics: Reference and Monitoring System
    7. 4.7  Electrical Characteristics: Buck Controllers
    8. 4.8  Electrical Characteristics: Synchronous Buck Converters
    9. 4.9  Electrical Characteristics: LDOs
    10. 4.10 Electrical Characteristics: Load Switches
    11. 4.11 Digital Signals: I2C Interface
    12. 4.12 Digital Input Signals (CTLx)
    13. 4.13 Digital Output Signals (IRQB, GPOx)
    14. 4.14 Timing Requirements
    15. 4.15 Switching Characteristics
    16. 4.16 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 SMPS Voltage Regulators
      1. 5.3.1 Controller Overview
      2. 5.3.2 Converter Overview
      3. 5.3.3 DVS
      4. 5.3.4 Decay
      5. 5.3.5 Current Limit
    4. 5.4 LDOs and Load Switches
      1. 5.4.1 VTT LDO
      2. 5.4.2 LDOA1-LDOA3
      3. 5.4.3 Load Switches
    5. 5.5 Power Goods (PGOOD or PG) and GPOs
    6. 5.6 Power Sequencing and VR Control
      1. 5.6.1 CTLx Sequencing
      2. 5.6.2 PG Sequencing
      3. 5.6.3 Enable Delay
      4. 5.6.4 Power Up Sequence
      5. 5.6.5 Power Down Sequence
      6. 5.6.6 Sleep State Entry and Exit
      7. 5.6.7 Emergency Shutdown
    7. 5.7 Device Functional Modes
      1. 5.7.1 Off Mode
      2. 5.7.2 Standby Mode
      3. 5.7.3 Active Mode
    8. 5.8 I2C Interface
      1. 5.8.1 F/S-Mode Protocol
    9. 5.9 Register Maps
      1. 5.9.1  Register Map Summary
      2. 5.9.2  DEVICEID: PMIC Device and Revision ID Register (offset = 1h) [reset = OTP-Programmable]
      3. 5.9.3  IRQ: PMIC Interrupt Register (offset = 2h) [reset = 0000 0000]
      4. 5.9.4  IRQ_MASK: PMIC Interrupt Mask Register (offset = 3h) [reset = 1111 1111]
      5. 5.9.5  PMICSTAT: PMIC Status Register (offset = 4h) [reset = 0000 0000]
      6. 5.9.6  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 5h) [reset = 0000 0000]
      7. 5.9.7  BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = OTP-Programmable]
      8. 5.9.8  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = OTP-Programmable]
      9. 5.9.9  BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = OTP-Programmable]
      10. 5.9.10 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = OTP-Programmable]
      11. 5.9.11 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = OTP-Programmable]
      12. 5.9.12 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = OTP-Programmable]
      13. 5.9.13 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = OTP-Programmable]
      14. 5.9.14 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = OTP-Programmable]
      15. 5.9.15 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = OTP-Programmable]
      16. 5.9.16 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = OTP-Programmable]
      17. 5.9.17 DISCHCTRL1: Discharge Control1 Register (offset = 40h) [reset = OTP-Programmable]
      18. 5.9.18 DISCHCTRL2: Discharge Control2 Register (offset = 41h) [reset = OTP-Programmable]
      19. 5.9.19 DISCHCTRL3: Discharge Control3 Register (offset = 42h) [reset = OTP-Programmable]
      20. 5.9.20 PG_DELAY1: Power Good Delay1 Register (offset = 43h) [reset = OTP-Programmable]
      21. 5.9.21 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
      22. 5.9.22 BUCK1SLPCTRL: BUCK1 Sleep Control Register (offset = 92h) [reset = OTP-Programmable]
      23. 5.9.23 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = OTP-Programmable]
      24. 5.9.24 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = OTP-Programmable]
      25. 5.9.25 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = OTP-Programmable]
      26. 5.9.26 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = OTP-Programmable]
      27. 5.9.27 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = OTP-Programmable]
      28. 5.9.28 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = OTP-Programmable]
      29. 5.9.29 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = OTP-Programmable]
      30. 5.9.30 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = OTP-Programmable]
      31. 5.9.31 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = OTP-Programmable]
      32. 5.9.32 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = OTP-Programmable]
      33. 5.9.33 PG_DELAY2: Power Good Delay2 Register (offset = 9Dh) [reset = OTP-Programmable]
      34. 5.9.34 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = OTP-Programmable]
      35. 5.9.35 I2C_RAIL_EN1: VR Pin Enable Override1 Register (offset = A0h) [reset = OTP-Programmable]
      36. 5.9.36 I2C_RAIL_EN2/GPOCTRL: VR Pin Enable Override2/GPO Control Register (offset = A1h) [reset = OTP-Programmable]
      37. 5.9.37 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = OTP-Programmable]
      38. 5.9.38 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = OTP-Programmable]
      39. 5.9.39 GPO1PG_CTRL1: GPO1 PG Control1 Register (offset = A4h) [reset = OTP-Programmable]
      40. 5.9.40 GPO1PG_CTRL2: GPO1 PG Control2 Register (offset = A5h) [reset = OTP-Programmable]
      41. 5.9.41 GPO4PG_CTRL1: GPO4 PG Control1 Register (offset = A6h) [reset = OTP-Programmable]
      42. 5.9.42 GPO4PG_CTRL2: GPO4 PG Control2 Register (offset = A7h) [reset = OTP-Programmable]
      43. 5.9.43 GPO2PG_CTRL1: GPO2 PG Control1 Register (offset = A8h) [reset = OTP-Programmable]
      44. 5.9.44 GPO2PG_CTRL2: GPO2 PG Control2 Register (offset = A9h) [reset = OTP-Programmable]
      45. 5.9.45 GPO3PG_CTRL1: GPO3 PG Control1 Register (offset = AAh) [reset = OTP-Programmable]
      46. 5.9.46 GPO3PG_CTRL2: GPO3 PG Control2 Register (offset = ABh) [reset = OTP-Programmable]
      47. 5.9.47 MISCSYSPG Register (offset = ACh) [reset = OTP-Programmable]
      48. 5.9.48 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = OTP-Programmable]
      49. 5.9.49 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0000 0000]
      50. 5.9.50 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0000 0000]
      51. 5.9.51 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0000 0000]
      52. 5.9.52 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0000 0000]
      53. 5.9.53 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0000 0000]
      54. 5.9.54 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
      55. 5.9.55 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0000 0000]
  6. 6 Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Typical Application
        1. 6.1.1.1 Design Requirements
        2. 6.1.1.2 Detailed Design Procedure
          1. 6.1.1.2.1 Controller Design Procedure
            1. 6.1.1.2.1.1 Selecting the Inductor
            2. 6.1.1.2.1.2 Selecting the Output Capacitors
            3. 6.1.1.2.1.3 Selecting the FETs
            4. 6.1.1.2.1.4 Bootstrap Capacitor
            5. 6.1.1.2.1.5 Setting the Current Limit
            6. 6.1.1.2.1.6 Selecting the Input Capacitors
          2. 6.1.1.2.2 Converter Design Procedure
            1. 6.1.1.2.2.1 Selecting the Inductor
            2. 6.1.1.2.2.2 Selecting the Output Capacitors
            3. 6.1.1.2.2.3 Selecting the Input Capacitors
          3. 6.1.1.2.3 LDO Design Procedure
        3. 6.1.1.3 Application Curves
    2. 6.2 VIN 5-V Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Design Procedure
        1. 6.2.2.1 Controller Design Procedure
          1. 6.2.2.1.1 Selecting the LC Output Filter
          2. 6.2.2.1.2 Selecting the FETs
          3. 6.2.2.1.3 Setting the Current Limit
          4. 6.2.2.1.4 Selecting the Input Capacitors
      3. 6.2.3 Application Curve
    3. 6.3 Do's and Don'ts
  7. 7 Power Supply Coupling and Bulk Capacitors
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Option Addendum
      1. 10.1.1 Packaging Information
      2. 10.1.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Detailed Description

5.1 Overview

The TPS650860 power-management integrated circuit (PMIC) provides a highly flexible and configurable power solution that can power a wide array of processors along with DDR3/DDR4 memory and other peripherals. Integrated in the PMIC are three step-down controllers (BUCK1, BUCK2, and BUCK6), three step-down converters (BUCK3, BUCK4, and BUCK5), a sink or source LDO (VTT LDO), three low-voltage VIN LDOs (LDOA1–LDOA3), and three load switches (SWA1, SWB1, and SWB2). With on-chip one-time programmable (OTP) memory, configuration of each rail for default output value, power-up sequence, fault handling, and power good mapping into a GPO pin are all conveniently flexible. All VRs have a built-in discharge resistor, and the value can be changed using the DISCHCNT1–DISCHCNT3 and LDOA1_CTRL registers. When enabling a VR, the PMIC automatically disconnects the discharge resistor for that rail without any I2C command. Table 5-1 summarizes the key characteristics of the voltage rails.

Table 5-1 Summary of Voltage Regulators

RAIL TYPE INPUT VOLTAGE (V) OUTPUT VOLTAGE RANGE (V) CURRENT (mA)
MIN MAX MIN TYP MAX
BUCK1 Step-down Controller 4.5 21 0.41 OTP-programmable 3.575 scalable
BUCK2 Step-down Controller 4.5 21 0.41 OTP-programmable 3.575 scalable
BUCK3 Step-down Converter 4.5 5.5 0.41 OTP-programmable 3.575 3000
BUCK4 Step-down Converter 4.5 5.5 0.41 OTP-programmable 3.575 3000
BUCK5 Step-down Converter 4.5 5.5 0.41 OTP-programmable 3.575 3000
BUCK6 Step-down Controller 4.5 21 0.41 OTP-programmable 3.575 scalable
LDOA1 LDO 4.5 5.5 0.7 OTP-programmable 3.3 200(1)
LDOA2 LDO 1.62 1.98 0.7 OTP-programmable 1.5 600
LDOA3 LDO 1.62 1.98 0.7 OTP-programmable 1.5 600
SWA1 Load Switch 0.5 3.3 300
SWB1/SWB2 Load Switch 0.5 3.3 300
VTT Sink and Source LDO BUCK6 output VBUCK6 / 2 500
(1) When powered from a 5-V supply through the DRV5V_2_A1 pin. Otherwise, max current is limited by max IOUT of LDO5.

5.2 Functional Block Diagram

TPS650860 BlockDiagram.gif Figure 5-1 PMIC Functional Block Diagram

5.3 SMPS Voltage Regulators

The buck controllers integrate gate drivers for external power stages with programmable current limit (set by an external resistor at ILIMx pin), which allows for optimal selection of external passive components based on the desired system load. The buck converters include integrated power stage and require a minimum number of pins for power input, inductor, and output voltage feedback input. Combined with high-frequency switching, all these features allow use of inductors in small form factor, thus reducing total-system cost and size.

BUCK1–BUCK6 have selectable auto- and forced-PWM mode through the BUCKx_MODE bit in the BUCKxCTRL register. In default auto mode, the VR automatically switches between PWM and PFM depending on the output load to maximize efficiency.

All controllers and converters can be set to default VOUT or dynamically voltage changing at any time. This means that the rails can be programmed for any VOUT by the factory, so the device starts up with the default voltage, or during operation the rail can be programmed to another operating VOUT while the rail is enable or disabled. There are two step sizes or ranges available for VOUT selection: 10-mV and 25-mV steps. The step-size range must be selected prior to use and must be programmed by the factory. It is not subject to programming or change during operation.

For the 10-mV step-size range VOUT options, refer to the Table 5-2. For the 25-mV step-size range VOUT options, refer to the Table 5-3.

Table 5-2 10-mV Step-Size VOUT Range

VID Bits VOUT VID Bits VOUT VID Bits VOUT
0000000 0 0101011 0.83 1010110 1.26
0000001 0.41 0101100 0.84 1010111 1.27
0000010 0.42 0101101 0.85 1011000 1.28
0000011 0.43 0101110 0.86 1011001 1.29
0000100 0.44 0101111 0.87 1011010 1.30
0000101 0.45 0110000 0.88 1011011 1.31
0000110 0.46 0110001 0.89 1011100 1.32
0000111 0.47 0110010 0.90 1011101 1.33
0001000 0.48 0110011 0.91 1011110 1.34
0001001 0.49 0110100 0.92 1011111 1.35
0001010 0.50 0110101 0.93 1100000 1.36
0001011 0.51 0110110 0.94 1100001 1.37
0001100 0.52 0110111 0.95 1100010 1.38
0001101 0.53 0111000 0.96 1100011 1.39
0001110 0.54 0111001 0.97 1100100 1.40
0001111 0.55 0111010 0.98 1100101 1.41
0010000 0.56 0111011 0.99 1100110 1.42
0010001 0.57 0111100 1.00 1100111 1.43
0010010 0.58 0111101 1.01 1101000 1.44
0010011 0.59 0111110 1.02 1101001 1.45
0010100 0.60 0111111 1.03 1101010 1.46
0010101 0.61 1000000 1.04 1101011 1.47
0010110 0.62 1000001 1.05 1101100 1.48
0010111 0.63 1000010 1.06 1101101 1.49
0011000 0.64 1000011 1.07 1101110 1.50
0011001 0.65 1000100 1.08 1101111 1.51
0011010 0.66 1000101 1.09 1110000 1.52
0011011 0.67 1000110 1.10 1110001 1.53
0011100 0.68 1000111 1.11 1110010 1.54
0011101 0.69 1001000 1.12 1110011 1.55
0011110 0.70 1001001 1.13 1110100 1.56
0011111 0.71 1001010 1.14 1110101 1.57
0100000 0.72 1001011 1.15 1110110 1.58
0100001 0.73 1001100 1.16 1110111 1.59
0100010 0.74 1001101 1.17 1111000 1.60
0100011 0.75 1001110 1.18 1111001 1.61
0100100 0.76 1001111 1.19 1111010 1.62
0100101 0.77 1010000 1.20 1111011 1.63
0100110 0.78 1010001 1.21 1111100 1.64
0100111 0.79 1010010 1.22 1111101 1.65
0101000 0.80 1010011 1.23 1111110 1.66
0101001 0.81 1010100 1.24 1111111 1.67
0101010 0.82 1010101 1.25

Table 5-3 25-mV Step-Size VOUT Range

VID Bits VOUT (Converters) VOUT (Controllers) VID Bits VOUT VID Bits VOUT
0000000 0 1.000 0101011 1.475 1010110 2.550
0000001 0.425 1.000 0101100 1.500 1010111 2.575
0000010 0.450 1.000 0101101 1.525 1011000 2.600
0000011 0.475 1.000 0101110 1.550 1011001 2.625
0000100 0.500 1.000 0101111 1.575 1011010 2.650
0000101 0.525 1.000 0110000 1.600 1011011 2.675
0000110 0.550 1.000 0110001 1.625 1011100 2.700
0000111 0.575 1.000 0110010 1.650 1011101 2.725
0001000 0.600 1.000 0110011 1.675 1011110 2.750
0001001 0.625 1.000 0110100 1.700 1011111 2.775
0001010 0.650 1.000 0110101 1.725 1100000 2.800
0001011 0.675 1.000 0110110 1.750 1100001 2.825
0001100 0.700 1.000 0110111 1.775 1100010 2.850
0001101 0.725 1.000 0111000 1.800 1100011 2.875
0001110 0.750 1.000 0111001 1.825 1100100 2.900
0001111 0.775 1.000 0111010 1.850 1100101 2.925
0010000 0.800 1.000 0111011 1.875 1100110 2.950
0010001 0.825 1.000 0111100 1.900 1100111 2.975
0010010 0.850 1.000 0111101 1.925 1101000 3.000
0010011 0.875 1.000 0111110 1.950 1101001 3.025
0010100 0.900 1.000 0111111 1.975 1101010 3.050
0010101 0.925 1.000 1000000 2.000 1101011 3.075
0010110 0.950 1.000 1000001 2.025 1101100 3.100
0010111 0.975 1.000 1000010 2.050 1101101 3.125
0011000 1.000 1.000 1000011 2.075 1101110 3.150
0011001 1.025 1.025 1000100 2.100 1101111 3.175
0011010 1.050 1.050 1000101 2.125 1110000 3.200
0011011 1.075 1.075 1000110 2.150 1110001 3.225
0011100 1.100 1.100 1000111 2.175 1110010 3.250
0011101 1.125 1.125 1001000 2.200 1110011 3.275
0011110 1.150 1.150 1001001 2.225 1110100 3.300
0011111 1.175 1.175 1001010 2.250 1110101 3.325
0100000 1.200 1.200 1001011 2.275 1110110 3.350
0100001 1.225 1.225 1001100 2.300 1110111 3.375
0100010 1.250 1.250 1001101 2.325 1111000 3.400
0100011 1.275 1.275 1001110 2.350 1111001 3.425
0100100 1.300 1.300 1001111 2.375 1111010 3.450
0100101 1.325 1.325 1010000 2.400 1111011 3.475
0100110 1.350 1.350 1010001 2.425 1111100 3.500
0100111 1.375 1.375 1010010 2.450 1111101 3.525
0101000 1.400 1.400 1010011 2.475 1111110 3.550
0101001 1.425 1.425 1010100 2.500 1111111 3.575
0101010 1.450 1.450 1010101 2.525

5.3.1 Controller Overview

The controllers are fast-reacting, high-frequency, scalable output power controllers capable of driving two external N-MOSFETs. They are D-CAP2 controller scheme that optimizes transient responses at high load currents for such applications as CORE and DDR supplies. The output voltage is compared with internal reference voltage after divider resistors. The PWM comparator determines the timing to turn on the high-side MOSFET. The PWM comparator response maintains a very small PWM output ripple voltage. Because the device does not have a dedicated oscillator for control loop on board, switching cycle is controlled by the adaptive on-time circuit. The on-time is controlled to meet the target switching frequency by feed-forwarding the input and output voltage into the on-time one-shot timer.

The D-CAP2 control scheme has an injected ripple from the SW node that is added on to the reference voltage to simulate output ripple, which eliminates the need for ESR-induced output ripple from D-CAP™ mode control. Thus, low-ESR output capacitors (such as low-cost ceramic MLCC capacitors) can be used with the controllers.

TPS650860 DCAP2_BlockDiagram.gif Figure 5-2 Controller Block Diagram

5.3.2 Converter Overview

The PMIC synchronous step-down DCDC converters include a unique hysteretic PWM controller scheme which enables a high switching frequency converter, excellent transient and AC load regulation as well as operation with cost-competitive external components. The controller topology supports forced PWM mode as well as power-save mode operation. Power-save mode operation, or PFM mode, reduces the quiescent current consumption and ensures high conversion efficiency at light loads by skipping switch pulses. In forced PWM mode, the device operates on a quasi-fixed frequency, avoids pulse skipping, and allows filtering of the switch noise by external filter components. The PMIC device offers fixed output voltage options featuring smallest solution size by using only three external components per converter.

A significant advantage of PMIC compared to other hysteretic PWM controller topologies is its excellent AC load transient regulation capability. When the output voltage falls below the threshold of the error comparator, a switch pulse is initiated, and the high-side switch is turned on. It remains turned on until a minimum ON-time of tONmin expires and the output voltage trips the threshold of the error comparator or the inductor current reaches the high-side switch current limit. When the high-side switch turns off, the low-side switch rectifier is turned on and the inductor current ramps down until the high-side switch turns on again or the inductor current reaches zero. In forced PWM mode operation, negative inductor current is allowed to enable continuous conduction mode even at no load condition.

TPS650860 DCS-Control_BlockDiagram.gif Figure 5-3 Converter Block Diagram

5.3.3 DVS

BUCK1–BUCK6 support dynamic voltage scaling (DVS) for maximum system efficiency. The VR outputs can slew up and down in either 10-mV or 25-mV steps using the 7-bit voltage ID (VID) defined in Section 4.7 and Section 4.8. DVS slew rate is minimum 2.5 mV/µs. In order to meet the minimum slew rate, VID progresses to the next code at 3-µs (nom) interval per 10-mV or at 6-µs interval per 25-mV steps. When DVS is active, the VR is forced into PWM mode, unless BUCKx_DECAY = 1, to ensure the output keeps track of VID code with minimal delay. Additionally, PGOOD is masked when DVS is in progress. An example of slew down and up from one VID to another (step size of 10 mV) is depicted in Figure 5-4.

TPS650860 DVS_td_public_swcs127.gif Figure 5-4 DVS Timing Diagram I (BUCKx_DECAY = 0)

As illustrated in Figure 5-5, if a BUCKx_VID[6:0] is set to 7b000 0000, its output voltage will slew down to 0.5 V first, and then will drift down to 0 V as the SMPS stops switching. Subsequently, if a BUCKx_VID[6:0] is set to a value (neither 7b000 0000 nor 7b000 0001) when its output voltage is less than 0.5 V, the VR will ramp up to 0.5 V first with soft-start kicking in, then will slew up to target voltage in the slew rate aforementioned. It must be noted that a fixed 200 µs of soft-start time is reserved for VOUT to reach 0.5 V. In this case, however, the SMPS is not forced into PWM mode as it otherwise could cause VOUT to droop momentarily if VOUT might have been drifting above 0.5 V for any reason.

TPS650860 BSW_DVS_TD2_public.gif Figure 5-5 DVS Timing Diagram II (BUCKx_DECAY = 0)

5.3.4 Decay

In addition to DVS, BUCK1–BUCK6 can decay down to a lower voltage when BUCKx_DECAY bit in BUCKxCTRL register is set to 1. Decay mode is only used in a downward direction of VID. The VR does not control slew rate. As both high-side and low-side FETs stop switching, the output voltage ramps down naturally, dictated by current drawn from the load and output filtering capacitance. When the VR is in the middle of decay down its PGOOD is masked until VOUT falls below the over-voltage (OV) threshold of the set VID value. Shown in Figure 5-6 are two cases that differ from each other as to whether VOUT has reached the target voltage corresponding to a new VID when the VR is commanded to slew back up to a higher voltage. In case that VOUT has not decayed down below VID as denoted case 2, the VR will wait for VID to catch up, and then VOUT will start ramping up to keep up with the VID ramp.

TPS650860 decay_lower_vout_slew_up_public_swcs127.gif Figure 5-6 Decay Down to a Lower VOUT and Slew Up
TPS650860 decay_0v_slew_up_public.gif Figure 5-7 Decay Down to 0 V and Slew Up

5.3.5 Current Limit

The buck controllers (BUCK1, BUCK2, and BUCK6) have inductor-valley current-limit architecture and the current limit is programmable by an external resistor at the ILIMx pin. Equation 1 shows the calculation for a desired resistor value, depending on specific application conditions. ILIMREF is the current source out of the ILIMx pin that is typically 50 µA, and RDSON is the maximum channel resistance of the low-side FET. the scaling factor is 1.3 to take into account all errors and temperature variations of RDSON, ILIMREF, and RILIM. Finally, 8 is another scaling factor associated with ILIMREF.

Equation 1. TPS650860 eq1_swcs127.gif

where

  • ILIM is the target current limit. An appropriate margin must be allowed when determining ILIM from maximum output DC load current.
  • Iripple,min is the minimum peak-to-peak inductor ripple current for a given VOUT.
Equation 2. TPS650860 eq2_swcs127.gif

where

  • Lmax is maximum inductance
  • fsw,max is maximum switching frequency
  • Vin,min minimum input voltage to the external power stage

The buck converter limit inductor peak current cycle-by-cycle to IIND_LIM is specified in Section 4.8.

5.4 LDOs and Load Switches

5.4.1 VTT LDO

Powered from the BUCK6 output , VTT LDO tracks VBUCK6 by regulating its output to a half of its input. The LDO is capable of sinking and sourcing current up to 500 mA, and it is designed specifically to power DDR memory. The LDO core is a transconductance amplifier with large gain, and it drives a current output stage that either sources or sinks current depending on the deviation of VTTFB pin voltage from the target regulation voltage.

5.4.2 LDOA1–LDOA3

The TPS65086x device integrates three general purpose LDOs. LDOA1 is powered from a 5-V supply through the DRV5V_2_A1 pin and it can be factory configured to be an Always-On rail as long as a valid power supply is available at VSYS. See Table 5-4 for LDOA1 output voltage options. LDOA2 and LDOA3 share a power input pin (PVINLDOA2_A3). The output regulation voltages are set by writing to LDOAx_VID[3:0] bits (Reg 0x9A, 0x9B, and 0xAE). See Table 5-5 for LDOA2 and LDOA3 output voltage options. LDOA1 is controlled by LDOA1CTRL register.

Table 5-4 LDOA1 Output Voltage Options

VID Bits VOUT VID Bits VOUT VID Bits VOUT VID Bits VOUT
0000 1.35 0100 1.8 1000 2.3 1100 2.85
0001 1.5 0101 1.9 1001 2.4 1101 3.0
0010 1.6 0110 2.0 1010 2.5 1110 3.3
0011 1.7 0111 2.1 1011 2.6 1111 Not Used

Table 5-5 LDOA2 and LDOA3 Output Voltage Options

VID Bits VOUT VID Bits VOUT VID Bits VOUT VID Bits VOUT
0000 0.70 0100 0.90 1000 1.10 1100 1.30
0001 0.75 0101 0.95 1001 1.15 1101 1.35
0010 0.80 0110 1.00 1010 1.20 1110 1.40
0011 0.85 0111 1.05 1011 1.25 1111 1.50

5.4.3 Load Switches

The PMIC features three general purpose load switches. SWA1 has its own power input pin (PVINSWA1), while SWB1 and SWB2 share one power input pin (PVINSWB1_B2). All switches have built-in slew rate control during startup to limit the inrush current.

5.5 Power Goods (PGOOD or PG) and GPOs

The device provides information on status of VRs through four GPO pins along with Power-Good Status registers defined in Section 5.9.49 and Section 5.9.50. Power-good information of any individual VR and load switch can be assigned to be part of the PGOOD tree as defined from Section 5.9.39 to Section 5.9.46. PGOOD assertion delays are programmable from 0 ms to 15 ms for GPO1 and 0 ms to 100 ms for GPO2–GPO4, respectively, as are defined in Section 5.9.20 and Section 5.9.33.

TPS650860 PowerGoodTree.gif Figure 5-8 Power Good Tree

Alternatively, the GPOs can be used as general purpose outputs controlled by the user via I²C. Refer to the I2C_RAIL_EN2/GPOCTRL Register Description for details on controlling the GPOs in I²C control mode.

5.6 Power Sequencing and VR Control

The device has 3 different ways of sequencing the rails during power up and power down:

  • Rail enabled by CTLx pin
  • Rail enabled by power good, (PG), of prior enabled rail
  • Rail enabled by I²C software command

A delay can be added from any CTLx pin or PG to the enable of the subjected enabled rail. This creates a very flexible device capable of many sequence options. If a rail cannot be sequenced automatically, any rail can be enabled or disabled via I2C command.

5.6.1 CTLx Sequencing

The device has six control-input pins (CTL1–CTL6) to control six SMPS regulators, three LDO regulators, and three load switches. This allows the user to define up to six distinctive groups, to which each VR can be assigned for highly flexible power sequencing. Of the six CTLx pins, CTL3 and CTL6 can be configured alternatively to active-low sleep enable pins. For instance, if a system level SLEEP state is defined such that BUCK1 output regulation voltage is lower than in the normal mode, then BUCK2 SLEEP state can be assigned to CTL3 or CTL6. By being pulled low, either CTL3 or CTL6 can be used to put BUCK1 into SLEEP state, and BUCK1 will regulate its output at a voltage defined by BUCK1_SLP_VID[6:0] in Section 5.9.22. In the example Section 5.6.4, see how the BUCK1 is enabled from CTL1 pin for a demonstration of this feature.

5.6.2 PG Sequencing

Any rail can be sequenced by the power good of a prior rail. This can be combined with the CTLx method to allow for further sequence control and create more distinctive groups of enables than the 6 from CTLx. This also allows some of the CTLx pins to be freed up for other purposes such as logic input gates. In the example Section 5.6.4, see how the BUCK5 is enabled from the BUCK4 PG for a demonstration of this feature.

5.6.3 Enable Delay

A delay can be added to the enable of any rail after the desired CTLx & PGs are met. This allows for the option to create additional timing groups from either CTLx pins or internal PGs. In the example Section 5.6.4, see how the BUCK2 and BUCK6 are enabled after BUCK1 from CTL1 pin for a demonstration of this feature.

5.6.4 Power Up Sequence

When a valid power supply is detected at the VSYS pin as VSYS crosses above VSYS_UVLO_5V + VSYS_UVLO+5V_HYS, the power-up sequence is initiated by driving one of the control input pins high, followed by the rest of pins in order. Illustrated in Figure 5-9 is an example where CTL1–CTL4 are defined to control four groups of VRs, while GPO1–GPO4 are defined to provide a PGOOD status of each group. The control input pins do not necessarily have to be pulled up in a staggered manner. For instance, if CTL2 is pulled up from the preceding group of VRs before PGOOD has been asserted at GPO1, the BUCK4 enable will be delayed until the PGOOD is asserted.

TPS650860 860_PowerUp.gif Figure 5-9 TPS650860 Power Up Sequence Example

5.6.5 Power Down Sequence

The power down sequence can follow the CTLx pins, or be controlled with the I²C commands. If the internal PGs are used for sequencing or if some rails need to ramp down before others a delay can be added to the de-assertion low of the internal enable of the subjected rail. This delay can be independent of the power up delay option. Thus, power up and power down sequences can be different of each other or relatively similar to match most applications' sequences.

Refer to Figure 5-10 for an example of a power down sequence demonstrating the delay disable of BUCK1 and BUCK2.

TPS650860 860_PowerDown.gif Figure 5-10 TPS650860 Power Down Sequence Example

5.6.6 Sleep State Entry and Exit

TPS650860 CAT_Sleep_Entry_Exit.gif Figure 5-11 Connected Standby Entry and Exit Sequence

Section 5.6.6 illustrates an example where BUCK1 is defined to enter Sleep State in response to CTL6 going low.

NOTE

All PGOODs from GPO1–GPO4 stay asserted during the entry and the exit. Depending on status of the BUCK1_DECAY bit defined in the BUCK1CTRL register, BUCK1 output will either decay or slew down to a new voltage defined in BUCK1_SLP_VID[6:0].

5.6.7 Emergency Shutdown

TPS650860 CAT_Emergency_Shutdown.gif Figure 5-12 Emergency Shutdown Sequence

When VSYS crosses below VSYS_UVLO_5V, all power good pins will be deasserted, and after 444 ns (nom) of delay all VRs will shut down. Upon shutdown, all internal discharge resistors are set to 100 Ω to ensure timely decay of all VR outputs. Other conditions that will cause emergency shutdown are the die temperature rising above the critical temperature threshold (TCRIT), and de-assertion of power good of any rail (configurable).

5.7 Device Functional Modes

5.7.1 Off Mode

When power supply at the VSYS pin is less than VSYS_UVLO_5V (5.4-V nominal) + VSYS_UVLO_5V_HYS (0.2-V nominal), the device is in off mode, where all output rails are disabled. If the supply voltage is greater than VSYS_UVLO_3V (3.6-V nominal) + VSYS_UVLO_3V_HYS (0.15-V nominal) while it is still less than VSYS_UVLO_5V + VSYS_UVLO_5V_HYS, then the internal bandgap reference (VREF pin) along with LDO3P3 are enabled and regulated at target values.

5.7.2 Standby Mode

When power supply at the VSYS pin rises above VSYS_UVLO_5V + VSYS_UVLO_5V_HYS, the device enters standby mode, where all internal reference and regulators (LDO3P3 and LDO5) are up and running, and I2C interface and CTL pins are ready to respond. All default registers defined in Section 5.9 should have been loaded from one-time programmable (OTP) memory by now. Quiescent current consumption in standby mode is specified in Section 4.5.

5.7.3 Active Mode

The device proceeds to active mode when any output rail is enabled either via an input pin as discussed in Section 5.6 or by writing to EN bits via I2C. Output regulation voltage can also be changed by writing to VID bits defined in Section 5.9.

5.8 I2C Interface

The I2C interface is a 2-wire serial interface developed by NXP™ (formerly Philips Semiconductor) (see I2C-Bus Specification and user manual, Rev 4, 13 February 2012). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, DATA and CLK. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device.

The TPS650860 device works as a slave and supports the following data transfer modes, as defined in the I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode
(1 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents are loaded when VSYS higher than VSYS_UVLO_5V is applied to the TPS650860 device. The I2C interface is running from an internal oscillator that is automatically enabled when there is an access to the interface.

The data transfer protocol for standard and fast modes are exactly the same, therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as H/S-mode.

The TPS650860 device supports 7-bit addressing; however, 10-bit addressing and general call address are not supported. The default device address is 0x5E.

5.8.1 F/S-Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high (see Figure 5-13). All I2C-compatible devices should recognize a start condition.

The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see
Figure 5-14). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 5-15), by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that the communication link with a slave has been established.

The master generates further SCL cycles to either transmit data to the slave (R/W bit = 0) or receive data from the slave (R/W bit = 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 5-13). This releases the bus and stops the communication link with the addressed slave. All I2C-compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address.

TPS650860 start_stop_conditions_swcs127.gif Figure 5-13 START and STOP Conditions
TPS650860 bit_transfer_swcs127.gif Figure 5-14 Bit Transfer on the I2C Bus
TPS650860 acknowledge_i2c_bus_swcs127.gif Figure 5-15 Acknowledge on the I2C Bus
TPS650860 I2c_bus_protocol_swcs127.gif Figure 5-16 I2C Bus Protocol
TPS650860 I2C_interface_write_swcs127.gif Figure 5-17 I2C Interface WRITE to TPS650860 in F/S Mode
TPS650860 I2C_interface_read_swcs127.gif Figure 5-18 I2C Interface READ from TPS650860 in F/S Mode
(Only Repeated START is Supported)

5.9 Register Maps

5.9.1 Register Map Summary

Table 5-6 Register Map Summary

Address Hex Value Name Short Description
1h DEVICEID Device ID code indicating revision
2h IRQ Interrupt statuses
3h IRQ_MASK Interrupt masking
4h PMIC_STAT PMIC temperature indicator
5h SHUTDNSRC Shutdown root cause indicator bits
20h BUCK1CTRL BUCK1 decay control and voltage select
21h BUCK2CTRL BUCK2 decay control and voltage select
22h BUCK3DECAY BUCK3 decay control
23h BUCK3VID BUCK3 voltage select
24h BUCK3SLPCTRL BUCK3 voltage select for sleep state
25h BUCK4CTRL BUCK4 control
26h BUCK5CTRL BUCK5 control
27h BUCK6CTRL BUCK6 control
28h LDOA2CTRL LDOA2 control
29h LDOA3CTRL LDOA3 control
40h DISCHCTRL1 Discharge resistors for each rail control
41h DISCHCTRL2 Discharge resistors for each rail control
42h DISCHCTRL3 Discharge resistors for each rail control
43h PG_DELAY1 System power good on GPO3 (if GPO3 is programmed to be system PG)
91h FORCESHUTDN Software force shutdown
92h BUCK1SLPCTRL BUCK1 voltage select for sleep state
93h BUCK2SLPCTRL BUCK2 voltage select for sleep state
94h BUCK4VID BUCK4 voltage select
95h BUCK4SLPVID BUCK4 voltage select for sleep state
96h BUCK5VID BUCK5 voltage select
97h BUCK5SLPVID BUCK5 voltage select for sleep state
98h BUCK6VID BUCK6 voltage select
99h BUCK6SLPVID BUCK6 voltage select for sleep state
9Ah LDOA2VID LDOA2 voltage select
9Bh LDOA3VID LDOA3 voltage select
9Ch BUCK123CTRL BUCK1, 2, and 3 disable and PFM/PWM mode control
9Dh PG_DELAY2 System power good on GPO1, 2, and 4 (if GPOs is programmed to be system PG)
9Fh SWVTT_DIS SWs & VTT I2C disable bits
A0h I2C_RAIL_EN1 I2C Enable control of individual rails
A1h I2C_RAIL_EN2/GPOCTRL I2C Enable control of individual rails and I2C controlled GPOs, high or low
A2h PWR_FAULT_MASK1 Power fault masking for individual rails
A3h PWR_FAULT_MASK2 Power fault masking for individual rails
A4h GPO1PG_CTRL1 Power good tree control for GPO1
A5h GPO1PG_CTRL2 Power good tree control for GPO1
A6h GPO4PG_CTRL1 Power good tree control for GPO4
A7h GPO4PG_CTRL2 Power good tree control for GPO4
A8h GPO2PG_CTRL1 Power good tree control for GPO2
A9h GPO2PG_CTRL2 Power good tree control for GPO2
AAh GPO3PG_CTRL1 Power good tree control for GPO3
ABh GPO3PG_CTRL2 Power good tree control for GPO3
ACh MISCSYSPG Power good tree control with CTL3 and CTL6 for GPO
AEh LDOA1CTRL LDOA1 control for discharge, voltage selection, and enable
B0h PGSTATUS1 Power good statuses for individual rails
B1h PGSTATUS2 Power good statuses for individual rails
B2h PWR_FAULT_STATUS1 Power fault statuses for individual rails
B3h PWR_FAULT_STATUS2 Power fault statuses for individual rails
B4h TEMPCRIT Critical temperature indicators
B5h TEMPHOT Hot temperature indicators

The user must not attempt to write a RESERVED R/W bit to the opposite value.

5.9.2 DEVICEID: PMIC Device and Revision ID Register (offset = 1h) [reset = OTP-Programmable]

Figure 5-19 DEVICEID Register
Bit 7 6 5 4 3 2 1 0
Bit Name REVID[1] REVID[0] OTP_
VERSION[1]		 OTP_
VERSION[0]		 PART_
NUMBER[3]		 PART_
NUMBER[2]		 PART_
NUMBER[1]		 PART_
NUMBER[0]
TPS650860 0 0 0 0 0 0 0 0
Access R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-7 DEVICEID Register Descriptions

Bit Field Type Reset Description
7-6 REVID[1:0] R OTP-Programmable Silicon revision ID
5-4 OTP_VERSION[1:0] R OTP-Programmable OTP variation ID
00: A
01: B
10: C
11: D
3-0 PART_NUMBER[3:0] R OTP-Programmable Device part number ID
0000: TPS650860
0001: TPS650861
...
1111: TPS65086F

5.9.3 IRQ: PMIC Interrupt Register (offset = 2h) [reset = 0000 0000]

Figure 5-20 IRQ Register
Bit 7 6 5 4 3 2 1 0
Bit Name FAULT RESERVED RESERVED RESERVED SHUTDN RESERVED RESERVED DIETEMP
TPS650860 0 0 0 0 0 0 0 0
Access R/W R R R R/W R R R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-8 IRQ Register Descriptions

Bit Field Type Reset Description
7 FAULT R/W 0 Fault interrupt. Asserted when either condition occurs: power fault of any rail, or die temperature crosses over the critical temperature threshold (TCRIT). The user can read Reg. 0xB2–0xB6 to determine what has caused the interrupt.
0: Not asserted
1: Asserted. Host to write 1 to clear.
3 SHUTDN R/W 0 Asserted when PMIC shuts down. To clear indicator, SHUTDNSRC must be cleared first, see Section 5.9.6
0: Not asserted.
1: Asserted. Host to write 1 to clear.
0 DIETEMP R/W 0 Die temp interrupt. Asserted when PMIC die temperature crosses above the hot temperature threshold (THOT).
0: Not asserted.
1: Asserted. Host to write 1 to clear.

5.9.4 IRQ_MASK: PMIC Interrupt Mask Register (offset = 3h) [reset = 1111 1111]

Figure 5-21 IRQ_MASK Register
Bit 7 6 5 4 3 2 1 0
Bit Name MFAULT RESERVED RESERVED RESERVED MSHUTDN RESERVED RESERVED MDIETEMP
TPS650860 1 1 1 1 1 1 1 1
Access R/W R R R R/W R R R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-9 IRQ_MASK Register Descriptions

Bit Field Type Reset Description
7 MFAULT R/W 1 FAULT interrupt mask.
0: Not masked.
1: Masked.
3 MSHUTDN R/W 1 PMIC shutdown event interrupt mask
0: Not masked.
1: Masked.
0 MDIETEMP R/W 1 Die temp interrupt mask.
0: Not masked.
1: Masked.

5.9.5 PMICSTAT: PMIC Status Register (offset = 4h) [reset = 0000 0000]

Figure 5-22 PMICSTAT Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SDIETEMP
TPS650860 0 0 0 0 0 0 0 0
Access R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-10 PMICSTAT Register Descriptions

Bit Field Type Reset Description
0 SDIETEMP R 0 PMIC die temperature status.
0: PMIC die temperature is below THOT.
1: PMIC die temperature is above THOT.

5.9.6 SHUTDNSRC: PMIC Shut-Down Event Register (offset = 5h) [reset = 0000 0000]

Figure 5-23 SHUTDNSRC Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED RESERVED RESERVED COLDOFF UVLO OCP CRITTEMP
TPS650860 0 0 0 0 0 0 0 0
Access R R R R R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-11 SHUTDNSRC Register Descriptions

Bit Field Type Reset Description
3 COLDOFF R/W 0 Set by PMIC cleared by host. Host to write 1 to clear. This bit is always 0 for TPS650860.
0 = Cleared
1= PMIC was shut down by pulling down CTL1 pin.
2 UVLO R/W 0 Set by PMIC cleared by host. Host to write 1 to clear.
0 = Cleared
1= PMIC was shut down due to a UVLO event (VSYS crosses below 5.4 V). Assertion of this bit sets the SHUTDN bit in Section 5.9.3.
1 OCP R/W 0 Set by PMIC cleared by host. Host to write 1 to clear.
0 = Cleared
1= PMIC was shut down due to an overcurrent event from BUCK1, BUCK2, BUCK6, or VTT LDO. Assertion of this bit sets the SHUTDN bit in Section 5.9.3.
0 CRITTEMP R/W 0 Set by PMIC cleared by host. Host to write 1 to clear.
0 = Cleared
1= PMIC was shut down due to the rise of PMIC die temperature above critical temperature threshold (TCRIT). Assertion of this bit sets the SHUTDN bit in Section 5.9.3.

5.9.7 BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = OTP-Programmable]

Figure 5-24 BUCK1CTRL Register
Bit 7 6 5 4 3 2 1 0
Bit Name BUCK1_
VID[6]		 BUCK1_
VID[5]		 BUCK1_
VID[4]		 BUCK1_
VID[3]		 BUCK1_
VID[2]		 BUCK1_
VID[1]		 BUCK1_
VID[0]		 BUCK1_
DECAY
TPS650860 1 0 0 0 0 0 1 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-12 BUCK1CTRL Register Descriptions

Bit Field Type Reset Description
7:1 BUCK1_VID[6:0] R/W OTP-Programmable This field sets the BUCK1 regulator output regulation voltage in normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.
0 BUCK1_DECAY R/W OTP-Programmable Decay Bit
0: The output slews down to a lower voltage set by the VID bits.
1: The output decays down to a lower voltage set by the VID bits. Decay rate depends on total capacitance and load present at the output.

5.9.8 BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = OTP-Programmable]

Figure 5-25 BUCK2CTRL Register (offset = 21h) [reset = OTP-Programmable]
Bit 7 6 5 4 3 2 1 0
Bit Name BUCK2_
VID[6]		 BUCK2_
VID[5]		 BUCK2_
VID[4]		 BUCK2_
VID[3]		 BUCK2_
VID[2]		 BUCK2_
VID[1]		 BUCK2_
VID[0]		 BUCK2_
DECAY
TPS650860 1 1 1 0 1 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-13 BUCK2CTRL Register Descriptions

Bit Field Type Reset Description
7:1 BUCK2_VID[6:0] R/W OTP-Programmable This field sets the BUCK2 regulator output regulation voltage in normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.
0 BUCK2_DECAY R/W OTP-Programmable Decay Bit
0: The output slews down to a lower voltage set by the VID bits.
1: The output decays down to a lower voltage set by the VID bits. Decay rate depends on total capacitance and load present at the output.

5.9.9 BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = OTP-Programmable]

Figure 5-26 BUCK3DECAY Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BUCK3_
DECAY
TPS650860 0 0 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-14 BUCK3DECAY Register Descriptions

Bit Field Type Reset Description
7:1 RESERVED R/W 0 Reserved
X: Reserved bit are do not care, can be 1 or 0.
0 BUCK3_DECAY R/W OTP-Programmable Decay Bit
0: The output slews down to a lower voltage set by the VID bits.
1: The output decays down to a lower voltage set by the VID bits. Decay rate depends on total capacitance and load present at the output.

5.9.10 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = OTP-Programmable]

Figure 5-27 BUCK3VID Register
Bit 7 6 5 4 3 2 1 0
Bit Name BUCK3_
VID[6]		 BUCK3_
VID[5]		 BUCK3_
VID[4]		 BUCK3_
VID[3]		 BUCK3_
VID[2]		 BUCK3_
VID[1]		 BUCK3_
VID[0]		 RESERVED
TPS650860 1 0 1 0 1 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-15 BUCK3VID Register Descriptions

Bit Field Type Reset Description
7:1 BUCK3_VID[6:0] R/W OTP-Programmable This field sets the BUCK3 regulator output regulation voltage in normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.

5.9.11 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = OTP-Programmable]

Figure 5-28 BUCK3SLPCTRL Register
Bit 7 6 5 4 3 2 1 0
Bit Name BUCK3_SLP
_ VID[6]		 BUCK3_SLP
_ VID[5]		 BUCK3_SLP
_ VID[4]		 BUCK3_SLP
_ VID[3]		 BUCK3_SLP
_ VID[2]		 BUCK3_SLP
_ VID[1]		 BUCK3_SLP
_ VID[0]		 BUCK3_SLP
_ EN
TPS650860 1 0 1 0 1 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-16 BUCK3SLPCTRL Register Descriptions

Bit Field Type Reset Description
7:1 BUCK3_SLP_VID[6:0] R/W OTP-Programmable This field sets the BUCK3 regulator output regulation voltage in sleep mode. BUCK3_SLP_VID bits are copied to BUCK3_VID bits upon enters sleep mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.
0 BUCK3_SLP_EN R/W OTP-Programmable BUCK3 sleep mode enable. For this bit to be effective, BUCK3 must be factory configured to enter sleep mode either by CTL3/SLPENB1 pin or by CTL6/SLPENB2 pin.
0: Disable.
1: Enable.

5.9.12 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = OTP-Programmable]

Figure 5-29 BUCK4CTRL Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BUCK4_
MODE		 BUCK4_DIS
TPS650860 0 0 1 1 1 1 0 1
Access R R R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-17 BUCK4CTRL Register Descriptions

Bit Field Type Reset Description
5:2 RESERVED R/W 1111 Reserved bits: Do not write to 0. These bits must stay 1 for sleep control reasons.
1 BUCK4_MODE R/W OTP-Programmable This field sets the BUCK4 regulator operating mode.
0 = Automatic mode
1 = Forced PWM mode
0 BUCK4_DIS R/W OTP-Programmable BUCK4 Disable Bit. Writing 0 to this bit forces BUCK4 to turn off regardless of any control input pin (CTL1–CTL6) status.
0: Disable
1: Enable

5.9.13 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = OTP-Programmable]

Figure 5-30 BUCK5CTRL Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BUCK5_
MODE		 BUCK5_DIS
TPS650860 0 0 1 1 1 1 0 1
Access R R R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-18 BUCK5CTRL Register Descriptions

Bit Field Type Reset Description
5:2 RESERVED R/W 1111 Reserved bits: Do not write to 0. These bits must stay 1 for sleep control reasons.
1 BUCK5_MODE R/W OTP-Programmable This field sets the BUCK5 regulator operating mode.
0 = Automatic mode
1 = Forced PWM mode
0 BUCK5_DIS R/W OTP-Programmable BUCK5 Disable Bit. Writing 0 to this bit forces BUCK5 to turn off regardless of any control input pin (CTL1–CTL6) status.
0: Disable.
1: Enable.

5.9.14 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = OTP-Programmable]

Figure 5-31 BUCK6CTRL Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BUCK6_
MODE		 BUCK6_DIS
TPS650860 0 0 1 1 1 1 0 1
Access R R R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-19 BUCK6CTRL Register Descriptions

Bit Field Type Reset Description
5:2 RESERVED R/W 1111 Reserved bits: Do not write to 0. These bits must stay 1 for sleep control reasons.
1 BUCK6_MODE R/W OTP-Programmable This field sets the BUCK6 regulator operating mode.
0 = Automatic mode
1 = Forced PWM mode
0 BUCK6_DIS R/W OTP-Programmable BUCK6 Disable Bit. Writing 0 to this bit forces BUCK6 to turn off regardless of any control input pin (CTL1–CTL6) status.
0: Disable.
1: Enable.

5.9.15 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = OTP-Programmable]

Figure 5-32 LDOA2CTRL Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED LDOA2_DIS
TPS650860 0 0 1 1 1 1 0 1
Access R R R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-20 LDOA2CTRL Register Descriptions

Bit Field Type Reset Description
5:2 RESERVED R/W 1111 Reserved bits: Do not write to 0. These bits must stay 1 for sleep control reasons.
0 LDOA2_DIS R/W OTP-Programmable LDOA2 Disable Bit. Writing 0 to this bit forces LDOA2 to turn off regardless of any control input pin (CTL1–CTL6) status.
0: Disable.
1: Enable.

5.9.16 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = OTP-Programmable]

Figure 5-33 LDOA3CTRL Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED LDOA3_DIS
TPS650860 0 0 1 1 1 1 0 1
Access R R R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-21 LDOA3CTRL Register Descriptions

Bit Field Type Reset Description
5:2 RESERVED R/W 1111 Reserved bits: Do not write to 0. These bits must stay 1 for sleep control reasons.
0 LDOA3_DIS R/W OTP-Programmable LDOA3 Disable Bit. Writing 0 to this bit forces LDOA3 to turn off regardless of any control input pin (CTL1–CTL6) status.
0: Disable
1: Enable

5.9.17 DISCHCTRL1: Discharge Control1 Register (offset = 40h) [reset = OTP-Programmable]

All xx_DISCHG[1:0] bits internally set to 00 whenever the corresponding VR is enabled.

Figure 5-34 DISCHCTRL1 Register
Bit 7 6 5 4 3 2 1 0
Bit Name BUCK4_
DISCHG[1]		 BUCK4_
DISCHG[0]		 BUCK3_
DISCHG[1]		 BUCK3_
DISCHG[0]		 BUCK2_
DISCHG[1]		 BUCK2_
DISCHG[0]		 BUCK1_
DISCHG[1]		 BUCK1_
DISCHG[0]
TPS650860 0 1 0 1 0 1 0 1
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-22 DISCHCTRL1 Register Descriptions

Bit Field Type Reset Description
7-6 BUCK4_DISCHG[1:0] R/W OTP-Programmable BUCK4 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
5-4 BUCK3_DISCHG[1:0] R/W OTP-Programmable BUCK3 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
3-2 BUCK2_DISCHG[1:0] R/W OTP-Programmable BUCK2 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
1-0 BUCK1_DISCHG[1:0] R/W OTP-Programmable BUCK1 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω

5.9.18 DISCHCTRL2: Discharge Control2 Register (offset = 41h) [reset = OTP-Programmable]

All xx_DISCHG[1:0] bits internally set to 00 whenever the corresponding VR is enabled.

Figure 5-35 DISCHCTRL2 Register
Bit 7 6 5 4 3 2 1 0
Bit Name LDOA2_
DISCHG[1]		 LDOA2_
DISCHG[0]		 SWA1_
DISCHG[1]		 SWA1_
DISCHG[0]		 BUCK6_
DISCHG[1]		 BUCK6_
DISCHG[0]		 BUCK5_
DISCHG[1]		 BUCK5_
DISCHG[0]
TPS650860 0 1 0 1 0 1 0 1
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-23 DISCHCTRL2 Register Descriptions

Bit Field Type Reset Description
7-6 LDOA2_DISCHG[1:0] R/W OTP-Programmable LDOA2 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
5-4 SWA1_DISCHG[1:0] R/W OTP-Programmable SWA1 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
3-2 BUCK6_DISCHG[1:0] R/W OTP-Programmable BUCK6 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
1-0 BUCK5_DISCHG[1:0] R/W OTP-Programmable BUCK5 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω

5.9.19 DISCHCTRL3: Discharge Control3 Register (offset = 42h) [reset = OTP-Programmable]

All xx_DISCHG[1:0] bits internally set to 00 whenever the corresponding VR is enabled.

Figure 5-36 DISCHCTRL3 Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED SWB2_
DISCHG[1]		 SWB2_
DISCHG[0]		 SWB1_
DISCHG[1]		 SWB1_
DISCHG[0]		 LDOA3_
DISCHG[1]		 LDOA3_
DISCHG[0]
TPS650860 0 0 0 1 0 1 0 1
Access R R R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-24 DISCHCTRL3 Register Descriptions

Bit Field Type Reset Description
5-4 SWB2_DISCHG[1:0] R/W OTP-Programmable SWB2 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
3-2 SWB1_DISCHG[1:0] R/W OTP-Programmable SWB1 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
1-0 LDOA3_DISCHG[1:0] R/W OTP-Programmable LDOA3 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω

5.9.20 PG_DELAY1: Power Good Delay1 Register (offset = 43h) [reset = OTP-Programmable]

Programmable Power Good delay for GPO3 pin, measured from the moment when all VRs assigned to GPO3 pin reach their regulation range to Power Good assertion. This is an optional register as the PMIC can be programmed for system PG, level shifter or I2C controller GPO.

Figure 5-37 PG_DELAY1 Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED RESERVED RESERVED RESERVED GPO3_PG_
DELAY[2]		 GPO3_PG_
DELAY[1]		 GPO3_PG_
DELAY[0]
TPS650860 0 0 0 0 0 1 1 1
Access R R R R R R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-25 PG_DELAY1 Register Descriptions

Bit Field Type Reset Description
2-0 GPO3_PG_DELAY[2:0] R/W OTP-Programmable Programmable delay power good or level shifter for GPO3 pin. Measured from the moment when all rails grouped to this pin reach their regulation range. All values have ±10 % variation
000 = 2.5 ms
001 = 5.0 ms
010 = 10 ms
011 = 15 ms
100 = 20 ms
101 = 50 ms
110 = 75 ms
111 = 100 ms
XXX = Register not used

5.9.21 FORCESHUTDN: Force Emergency Shutdown Control Register
(offset = 91h) [reset = 0000 0000]

Figure 5-38 FORCESHUTDN Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SDWN
TPS650860 0 0 0 0 0 0 0 0
Access R R R R R R R R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-26 FORCESHUTDN Register Descriptions

Bit Field Type Reset Description
0 SDWN R/W 0 Forces reset of the PMIC and reset of all registers. The bit is self-clearing.
0 = No action.
1 = PMIC is forced to shut down.

5.9.22 BUCK1SLPCTRL: BUCK1 Sleep Control Register (offset = 92h) [reset = OTP-Programmable]

Figure 5-39 BUCK1SLPCTRL Register
Bit 7 6 5 4 3 2 1 0
Bit Name BUCK1_
SLP_ VID[6]		 BUCK1_
SLP_ VID[5]		 BUCK1_
SLP_ VID[4]		 BUCK1_
SLP_ VID[3]		 BUCK1_
SLP_ VID[2]		 BUCK1_
SLP_ VID[1]		 BUCK1_
SLP_ VID[0]		 BUCK1_
SLP_ EN
TPS650860 1 0 0 0 0 0 1 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-27 BUCK1SLPCTRL Register Descriptions

Bit Field Type Reset Description
7:1 BUCK1_SLP_VID[6:0] R/W OTP-Programmable This field sets the BUCK1 regulator output regulation voltage in sleep mode. Mapping between bits and output voltage is defined as in Section 5.9.7.
0 BUCK1_SLP_EN R/W OTP-Programmable BUCK1 sleep mode enable. For this bit to be effective, BUCK1 must be factory configured to enter sleep mode either by CTL3/SLPENB1 pin or by CTL6/SLPENB2 pin.
0: Disable.
1: Enable.

5.9.23 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = OTP-Programmable]

Figure 5-40 BUCK2SLPCTRL Register
Bit 7 6 5 4 3 2 1 0
Bit Name BUCK2_SLP
_ VID[6]		 BUCK2_SLP
_ VID[5]		 BUCK2_SLP
_ VID[4]		 BUCK2_SLP
_ VID[3]		 BUCK2_SLP
_ VID[2]		 BUCK2_SLP
_ VID[1]		 BUCK2_SLP
_ VID[0]		 BUCK2_SLP
_ EN
TPS650860 1 1 1 0 1 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-28 BUCK2SLPCTRL Register Descriptions

Bit Field Type Reset Description
7:1 BUCK2_SLP_VID[6:0] R/W OTP-Programmable This field sets the BUCK2 regulator output regulation voltage in sleep mode. Mapping between bits and output voltage is defined as in Section 5.9.8.
0 BUCK2_SLP_EN R/W OTP-Programmable BUCK2 sleep mode enable. For this bit to be effective, BUCK2 must be factory configured to enter sleep mode either by CTL3/SLPENB1 pin or by CTL6/SLPENB2 pin.
0: Disable.
1: Enable.

5.9.24 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = OTP-Programmable]

Figure 5-41 BUCK4VID Register
Bit 7 6 5 4 3 2 1 0
Bit Name BUCK4_
VID[6]		 BUCK4_
VID[5]		 BUCK4_
VID[4]		 BUCK4_
VID[3]		 BUCK4_
VID[2]		 BUCK4_
VID[1]		 BUCK4_
VID[0]		 BUCK4_
DECAY
TPS650860 1 1 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-29 BUCK4VID Register Descriptions

Bit Field Type Reset Description
7:1 BUCK4_VID[6:0] R/W OTP-Programmable This field sets the BUCK4 regulator output regulation voltage in normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.
0 BUCK4_DECAY R/W OTP-Programmable Decay Bit
0: The output slews down to a lower voltage set by the VID bits.
1: The output decays down to a lower voltage set by the VID bits. Decay rate depends on total capacitance and load present at the output.

5.9.25 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = OTP-Programmable]

Figure 5-42 BUCK4SLPVID Register
Bit 7 6 5 4 3 2 1 0
Bit Name BUCK4_SLP
_ VID[6]		 BUCK4_SLP
_ VID[5]		 BUCK4_SLP
_ VID[4]		 BUCK4_SLP
_ VID[3]		 BUCK4_SLP
_ VID[2]		 BUCK4_SLP
_ VID[1]		 BUCK4_SLP
_ VID[0]		 RESERVED
TPS650860 1 1 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-30 BUCK4SLPVID Register Descriptions

Bit Field Type Reset Description
7:1 BUCK4_SLP_VID[6:0] R/W OTP-Programmable This field sets the BUCK4 regulator output regulation voltage in sleep mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.

5.9.26 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = OTP-Programmable]

Figure 5-43 BUCK5VID Register
Bit 7 6 5 4 3 2 1 0
Bit Name BUCK5_
VID[6]		 BUCK5_
VID[5]		 BUCK5_
VID[4]		 BUCK5_
VID[3]		 BUCK5_
VID[2]		 BUCK5_
VID[1]		 BUCK5_
VID[0]		 BUCK5_
DECAY
TPS650860 0 1 1 1 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-31 BUCK5VID Register Descriptions

Bit Field Type Reset Description
7:1 BUCK5_VID[6:0] R/W OTP-Programmable This field sets the BUCK5 regulator output regulation voltage in normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.
0 BUCK5_DECAY R/W OTP-Programmable Decay Bit
0: The output slews down to a lower voltage set by the VID bits.
1: The output decays down to a lower voltage set by the VID bits. Decay rate depends on total capacitance and load present at the output.

5.9.27 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = OTP-Programmable]

Figure 5-44 BUCK5SLPVID Register
Bit 7 6 5 4 3 2 1 0
Bit Name BUCK5_SLP
_ VID[6]		 BUCK5_SLP
_ VID[5]		 BUCK5_SLP
_ VID[4]		 BUCK5_SLP
_ VID[3]		 BUCK5_SLP
_ VID[2]		 BUCK5_SLP
_ VID[1]		 BUCK5_SLP
_ VID[0]		 RESERVED
TPS650860 0 1 1 1 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-32 BUCK5SLPVID Register Descriptions

Bit Field Type Reset Description
7:1 BUCK5_SLP_VID[6:0] R/W OTP-Programmable This field sets the BUCK5 regulator output regulation voltage in sleep mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.

5.9.28 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = OTP-Programmable]

Figure 5-45 BUCK6VID Register
Bit 7 6 5 4 3 2 1 0
Bit Name BUCK6_
VID[6]		 BUCK6_
VID[5]		 BUCK6_
VID[4]		 BUCK6_
VID[3]		 BUCK6_
VID[2]		 BUCK6_
VID[1]		 BUCK6_
VID[0]		 BUCK6_
DECAY
TPS650860 1 1 0 1 1 1 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-33 BUCK6VID Register Descriptions

Bit Field Type Reset Description
7:1 BUCK6_VID[6:0] R/W OTP-Programmable This field sets the BUCK6 regulator output regulation voltage in normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.
0 BUCK6_DECAY R/W OTP-Programmable Decay Bit
0: The output slews down to a lower voltage set by the VID bits.
1: The output decays down to a lower voltage set by the VID bits. Decay rate depends on total capacitance and load present at the output.

5.9.29 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = OTP-Programmable]

Figure 5-46 BUCK6SLPVID Register
Bit 7 6 5 4 3 2 1 0
Bit Name BUCK6_SLP
_ VID[6]		 BUCK6_SLP
_ VID[5]		 BUCK6_SLP
_ VID[4]		 BUCK6_SLP
_ VID[3]		 BUCK6_SLP
_ VID[2]		 BUCK6_SLP
_ VID[1]		 BUCK6_SLP
_ VID[0]		 RESERVED
TPS650860 1 1 0 1 1 1 0 0
Access R/W R/W R/W R/W R/W R/W R/W R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-34 BUCK6SLPVID Register Descriptions

Bit Field Type Reset Description
7:1 BUCK6_SLP_VID[6:0] R/W OTP-Programmable This field sets the BUCK6 regulator output regulation voltage in normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.

5.9.30 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = OTP-Programmable]

Figure 5-47 LDOA2VID Register
Bit 7 6 5 4 3 2 1 0
Bit Name LDOA2_SLP_
VID[3]		 LDOA2_SLP_
VID[2]		 LDOA2_SLP_
VID[1]		 LDOA2_SLP_
VID[0]		 LDOA2_
VID[3]		 LDOA2_
VID[3]		 LDOA2_
VID[1]		 LDOA2_
VID[0]
TPS650860 0 0 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-35 LDOA2VID Register Descriptions

Bit Field Type Reset Description
7-4 LDOA2_SLP_VID[3:0] R/W OTP-Programmable This field sets the LDOA2 regulator output regulation voltage in sleep mode.
See Table 5-5 for Vout options.
3-0 LDOA2_VID[3:0] R/W OTP-Programmable This field sets the LDOA2 regulator output regulation voltage in normal mode.
See Table 5-5 for Vout options.

5.9.31 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = OTP-Programmable]

Figure 5-48 LDOA3VID Register
Bit 7 6 5 4 3 2 1 0
Bit Name LDOA3_SLP
_ VID[3]		 LDOA3_SLP
_ VID[2]		 LDOA3_SLP
_ VID[1]		 LDOA3_SLP
_ VID[0]		 LDOA3_
VID[3]		 LDOA3_
VID[3]		 LDOA3_
VID[1]		 LDOA3_
VID[0]
TPS650860 1 0 1 0 1 0 1 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-36 LDOA3VID Register Descriptions

Bit Field Type Reset Description
7-4 LDOA3_SLP_VID[3:0] R/W OTP-Programmable This field sets the LDOA3 regulator output regulation voltage in sleep mode.
See Table 5-5 for Vout options.
3-0 LDOA3_VID[3:0] R/W OTP-Programmable This field sets the LDOA3 regulator output regulation voltage in normal mode.
See Table 5-5 for Vout options.

5.9.32 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = OTP-Programmable]

Figure 5-49 BUCK123CTRL Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED BUCK3
_MODE		 BUCK2
_MODE		 BUCK1
_MODE		 BUCK3
_DIS		 BUCK2
_DIS		 BUCK1
_DIS
TPS650860 0 0 0 0 0 1 1 1
Access R R R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-37 BUCK123CTRL Register Descriptions

Bit Field Type Reset Description
5 BUCK3_MODE R/W OTP-Programmable This field sets the BUCK3 regulator operating mode.
0 = Automatic mode
1 = Forced PWM mode
4 BUCK2_MODE R/W OTP-Programmable This field sets the BUCK2 regulator operating mode.
0 = Automatic mode
1 = Forced PWM mode
3 BUCK1_MODE R/W OTP-Programmable This field sets the BUCK1 regulator operating mode.
0 = Automatic mode
1 = Forced PWM mode
2 BUCK3_DIS R/W OTP-Programmable BUCK3 Disable Bit. Writing 0 to this bit forces BUCK3 to turn off regardless of any control input pin (CTL1–CTL6) status.
0: Disable
1: Enable
1 BUCK2_DIS R/W OTP-Programmable BUCK2 Disable Bit. Writing 0 to this bit forces BUCK2 to turn off regardless of any control input pin (CTL1–CTL6) status.
0: Disable
1: Enable
0 BUCK1_DIS R/W OTP-Programmable BUCK1 Disable Bit. Writing 0 to this bit forces BUCK1 to turn off regardless of any control input pin (CTL1–CTL6) status.
0: Disable
1: Enable

5.9.33 PG_DELAY2: Power Good Delay2 Register (offset = 9Dh) [reset = OTP-Programmable]

Programmable Power Good delay for GPO3 pin, measured from the moment when all VRs assigned to GPO3 pin reach their regulation range to Power Good assertion. This is an optional register as the PMIC can be programmed for system PG, level shifter or I2C controller GPO.

Figure 5-50 PG_DELAY2 Register
Bit 7 6 5 4 3 2 1 0
Bit Name GPO2_PG_
DELAY[2]		 GPO2_PG_
DELAY[1]		 GPO2_PG_
DELAY[0]		 GPO4_PG_
DELAY[2]		 GPO4_PG_
DELAY[1]		 GPO4_PG_
DELAY[0]		 GPO1_PG_
DELAY[1]		 GPO1_PG_
DELAY[0]
TPS650860 0 0 0 1 0 0 1 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-38 PG_DELAY2 Register Descriptions

Bit Field Type Reset Description
7-5 GPO2_PG_DELAY[2:0] R/W OTP-Programmable Programmable delay power good or level shifter for GPO2 pin. Measured from the moment when all rails grouped to this pin reach their regulation range. All values have ±10 % variation
000 = 2.5 ms
001 = 5.0 ms
010 = 10 ms
011 = 15 ms
100 = 20 ms
101 = 50 ms
110 = 75 ms
111 = 100 ms
4-2 GPO4_PG_DELAY[2:0] R/W OTP-Programmable Programmable delay power good or level shifter for GPO4 pin. Measured from the moment when all rails grouped to this pin reach their regulation range. All values have ±10 % variation
000 = 2.5 ms
001 = 5.0 ms
010 = 10 ms
011 = 15 ms
100 = 20 ms
101 = 50 ms
110 = 75 ms
111 = 100 ms
1-0 GPO1_PG_DELAY[1:0] R/W OTP-Programmable Programmable delay power good or level shifter for GPO1 pin. Measured from the moment when all rails grouped to this pin reach their regulation range. All values have ±10 % variation
00 = 0 ms
01 = 5.0 ms
10 = 10 ms
11 = 15 ms

5.9.34 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = OTP-Programmable]

Figure 5-51 SWVTT_DIS Register
Bit 7 6 5 4 3 2 1 0
Bit Name SWB2_DIS SWB1_DIS SWA1_DIS VTT_DIS Reserved Reserved Reserved Reserved
TPS650860 1 1 1 1 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-39 SWVTT_DIS Register Descriptions

Bit Field Type Reset Description
7 SWB2_DIS R/W OTP-Programmable SWB2 Disable Bit. Writing 0 to this bit forces SWB2 to turn off regardless of any control input pin (CTL1–CTL6) status.
0: Disable.
1: Enable.
6 SWB1_DIS R/W OTP-Programmable SWB1 Disable Bit. Writing 0 to this bit forces SWB1 to turn off regardless of any control input pin (CTL1–CTL6) status.
0: Disable.
1: Enable.
5 SWA1_DIS R/W OTP-Programmable SWA1 Disable Bit. Writing 0 to this bit forces SWA1 to turn off regardless of any control input pin (CTL1–CTL6) status.
0: Disable.
1: Enable.
4 VTT_DIS R/W OTP-Programmable VTT Disable Bit. Writing 0 to this bit forces VTT to turn off regardless of any control input pin (CTL1–CTL6) status.
0: Disable.
1: Enable.
3 Reserved R/W 0 Reserved, Keep bit 0 at all times. Do not write to 1.
2 Reserved R/W 0 Reserved, Keep bit 0 at all times. Do not write to 1.
1 Reserved R/W 0 Reserved, Keep bit 0 at all times. Do not write to 1.
0 Reserved R/W 0 Reserved, Keep bit 0 at all times. Do not write to 1.

5.9.35 I2C_RAIL_EN1: VR Pin Enable Override1 Register (offset = A0h) [reset = OTP-Programmable]

Figure 5-52 I2C_RAIL_EN1 Register
Bit 7 6 5 4 3 2 1 0
Bit Name LDOA2_EN SWA1_EN BUCK6_EN BUCK5_EN BUCK4_EN BUCK3_EN BUCK2_EN BUCK1_EN
TPS650860 0 0 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-40 I2C_RAIL_EN1 Register Descriptions

Bit Field Type Reset Description
7 LDOA2_EN R/W OTP-Programmable LDOA2 I2C Enable
0: LDOA2 is enabled or disabled by one of the control input pins or internal PG signal.
1: LDOA2 is forced on unless LDOA2_DIS = 0.
6 SWA1_EN R/W OTP-Programmable SWA1 I2C Enable
0: SWA1 is enabled or disabled by one of the control input pins or internal PG signal.
1: SWA1 is forced on unless SWA1_DIS = 0.
5 BUCK6_EN R/W OTP-Programmable BUCK6 I2C Enable
0: BUCK6 is enabled or disabled by one of the control input pins or internal PG signal.
1: BUCK6 is forced on unless BUCK6_DIS = 0.
4 BUCK5_EN R/W OTP-Programmable BUCK5 I2C Enable
0: BUCK5 is enabled or disabled by one of the control input pins or internal PG signal.
1: BUCK5 is forced on unless BUCK5_DIS = 0.
3 BUCK4_EN R/W OTP-Programmable BUCK4 I2C Enable
0: BUCK4 is enabled or disabled by one of the control input pins or internal PG signal.
1: BUCK4 is forced on unless BUCK4_DIS = 0.
2 BUCK3_EN R/W OTP-Programmable BUCK3 I2C Enable
0: BUCK3 is enabled or disabled by one of the control input pins or internal PG signal.
1: BUCK3 is forced on unless BUCK3_DIS = 0.
1 BUCK2_EN R/W OTP-Programmable BUCK2 I2C Enable
0: BUCK2 is enabled or disabled by one of the control input pins or internal PG signal.
1: BUCK2 is forced on unless BUCK2_DIS = 0.
0 BUCK1_EN R/W OTP-Programmable BUCK1 I2C Enable
0: BUCK1 is enabled or disabled by one of the control input pins or internal PG signal.
1: BUCK1 is forced on unless BUCK1_DIS = 0.

5.9.36 I2C_RAIL_EN2/GPOCTRL: VR Pin Enable Override2/GPO Control Register (offset = A1h) [reset = OTP-Programmable]

Figure 5-53 I2C_RAIL_EN2/GPOCTRL Register
Bit 7 6 5 4 3 2 1 0
Bit Name GPO4_LVL GPO3_LVL GPO2_LVL GPO1_LVL VTT_EN SWB2_EN SWB1_EN LDOA3_EN
TPS650860 X X 0 1 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-41 I2C_RAIL_EN2/GPOCTRL Register Descriptions

Bit Field Type Reset Description
7 GPO4_LVL R/W OTP-Programmable The field is to set GPO4 pin output if the pin is factory-configured as an open-drain general-purpose output.
0: The pin is driven to logic low.
1: The pin is driven to logic high.
X: Bit not used or is do not care for this version.
6 GPO3_LVL R/W OTP-Programmable The field is to set GPO3 pin output if the pin is factory-configured as either an open-drain or a push-pull general-purpose output.
0: The pin is driven to logic low.
1: The pin is driven to logic high.
X: Bit not used or is do not care for this version.
5 GPO2_LVL R/W OTP-Programmable The field is to set GPO2 pin output if the pin is factory-configured as either an open-drain or a push-pull general-purpose output.
0: The pin is driven to logic low.
1: The pin is driven to logic high.
4 GPO1_LVL R/W OTP-Programmable The field is to set GPO1 pin output if the pin is factory-configured as either an open-drain or a push-pull general-purpose output.
0: The pin is driven to logic low.
1: The pin is driven to logic high.
3 VTT_EN R/W OTP-Programmable VTT LDO I2C Enable
0: VTT LDO is enabled or disabled by one of the control input pins or internal PG signals.
1: VTT LDO is forced on unless VTT_DIS = 0.
2 SWB2_EN R/W OTP-Programmable SWB2 I2C Enable
0: SWB2 is enabled or disabled by one of the control input pins or internal PG signals.
1: SWB2 is forced on unless SWB2_DIS = 0.
1 SWB1_EN R/W OTP-Programmable SWB1 I2C Enable
0: SWB1 is enabled or disabled by one of the control input pins or internal PG signals.
1: SWB1 is forced on unless SWB1_DIS = 0.
0 LDOA3_EN R/W OTP-Programmable LDOA3 I2C Enable
0: LDOA3 is enabled or disabled by one of the control input pins or internal PG signals.
1: LDOA3 is forced on unless LDOA3_DIS = 0.

5.9.37 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = OTP-Programmable]

Figure 5-54 PWR_FAULT_MASK1 Register
Bit 7 6 5 4 3 2 1 0
Bit Name LDOA2_
FLTMSK		 SWA1_
FLTMSK		 BUCK6_
FLTMSK		 BUCK5_
FLTMSK		 BUCK4_
FLTMSK		 BUCK3_
FLTMSK		 BUCK2_
FLTMSK		 BUCK1_
FLTMSK
TPS650860 1 1 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-42 PWR_FAULT_MASK1 Register Descriptions

Bit Field Type Reset Description
7 LDOA2_FLTMSK R/W OTP-Programmable LDOA2 Power Fault Mask. When masked, power fault from LDOA2 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
6 SWA1_FLTMSK R/W OTP-Programmable SWA1 Power Fault Mask. When masked, power fault from SWA1 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
5 BUCK6_FLTMSK R/W OTP-Programmable BUCK6 Power Fault Mask. When masked, power fault from BUCK6 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
4 BUCK5_FLTMSK R/W OTP-Programmable BUCK5 Power Fault Mask. When masked, power fault from BUCK5 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
3 BUCK4_FLTMSK R/W OTP-Programmable BUCK4 Power Fault Mask. When masked, power fault from BUCK4 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
2 BUCK3_FLTMSK R/W OTP-Programmable BUCK3 Power Fault Mask. When masked, power fault from BUCK3 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
1 BUCK2_FLTMSK R/W OTP-Programmable BUCK2 Power Fault Mask. When masked, power fault from BUCK2 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
0 BUCK1_FLTMSK R/W OTP-Programmable BUCK1 Power Fault Mask. When masked, power fault from BUCK1 does not cause PMIC to shutdown.
0: Not Masked
1: Masked

5.9.38 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = OTP-Programmable]

Figure 5-55 PWR_FAULT_MASK2 Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED RESERVED LDOA1_
FLTMSK		 VTT_
FLTMSK		 SWB2_
FLTMSK		 SWB1_
FLTMSK		 LDOA3_
FLTMSK
TPS650860 0 0 1 0 0 1 1 0
Access R R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-43 PWR_FAULT_MASK2 Register Descriptions

Bit Field Type Reset Description
4 LDOA1_FLTMSK R/W OTP-Programmable LDOA1 Power Fault Mask. When masked, power fault from LDOA1 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
3 VTT_FLTMSK R/W OTP-Programmable VTT LDO Power Fault Mask. When masked, power fault from VTT LDO does not cause PMIC to shutdown.
0: Not Masked
1: Masked
2 SWB2_FLTMSK R/W OTP-Programmable SWB2 Power Fault Mask. When masked, power fault from SWB2 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
1 SWB1_FLTMSK R/W OTP-Programmable SWB1 Power Fault Mask. When masked, power fault from SWB1 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
0 LDOA3_FLTMSK R/W OTP-Programmable LDOA3 Power Fault Mask. When masked, power fault from LDOA3 does not cause PMIC to shutdown.
0: Not Masked
1: Masked

5.9.39 GPO1PG_CTRL1: GPO1 PG Control1 Register (offset = A4h) [reset = OTP-Programmable]

Figure 5-56 GPO1PG_CTRL1 Register
Bit 7 6 5 4 3 2 1 0
Bit Name LDOA2
_MSK		 RESERVED BUCK6
_MSK		 BUCK5
_MSK		 BUCK4
_MSK		 BUCK3
_MSK		 BUCK2
_MSK		 BUCK1
_MSK
TPS650860 1 1 1 1 1 1 1 1
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-44 GPO1PG_CTRL1 Register Descriptions

Bit Field Type Reset Description
7 LDOA2_MSK R/W OTP-Programmable 0: LDOA2 PG is part of Power Good tree of GPO1 pin.
1: LDOA2 PG is NOT part of Power Good tree of GPO1 pin and is ignored.
5 BUCK6_MSK R/W OTP-Programmable 0: BUCK6 PG is part of Power Good tree of GPO1 pin.
1: BUCK6 PG is NOT part of Power Good tree of GPO1 pin and is ignored.
4 BUCK5_MSK R/W OTP-Programmable 0: BUCK5 PG is part of Power Good tree of GPO1 pin.
1: BUCK5 PG is NOT part of Power Good tree of GPO1 pin and is ignored.
3 BUCK4_MSK R/W OTP-Programmable 0: BUCK4 PG is part of Power Good tree of GPO1 pin.
1: BUCK4 PG is NOT part of Power Good tree of GPO1 pin and is ignored.
2 BUCK3_MSK R/W OTP-Programmable 0: BUCK3 PG is part of Power Good tree of GPO1 pin.
1: BUCK3 PG is NOT part of Power Good tree of GPO1 pin and is ignored.
1 BUCK2_MSK R/W OTP-Programmable 0: BUCK2 PG is part of Power Good tree of GPO1 pin.
1: BUCK2 PG is NOT part of Power Good tree of GPO1 pin and is ignored.
0 BUCK1_MSK R/W OTP-Programmable 0: BUCK1 PG is part of Power Good tree of GPO1 pin.
1: BUCK1 PG is NOT part of Power Good tree of GPO1 pin and is ignored.

5.9.40 GPO1PG_CTRL2: GPO1 PG Control2 Register (offset = A5h) [reset = OTP-Programmable]

Figure 5-57 GPO1PG_CTRL2 Register
Bit 7 6 5 4 3 2 1 0
Bit Name CTL5_MSK CTL4_MSK CTL2_MSK CTL1_MSK VTT_MSK RESERVED RESERVED LDOA3_MSK
TPS650860 1 1 1 1 1 1 1 1
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-45 GPO1PG_CTRL2 Register Descriptions

Bit Field Type Reset Description
7 CTL5_MSK R/W OTP-Programmable 0: CTL5 pin status is part of Power Good tree of GPO1 pin.
1: CTL5 pin status is NOT part of Power Good tree of GPO1 pin and is ignored.
6 CTL4_MSK R/W OTP-Programmable 0: CTL4 pin status is part of Power Good tree of GPO1 pin.
1: CTL4 pin status is NOT part of Power Good tree of GPO1 pin and is ignored.
5 CTL2_MSK R/W OTP-Programmable 0: CTL2 pin status is part of Power Good tree of GPO1 pin.
1: CTL2 pin status is NOT part of Power Good tree of GPO1 pin and is ignored.
4 CTL1_MSK R/W OTP-Programmable 0: CTL1 pin status is part of Power Good tree of GPO1 pin.
1: CTL1 pin status is NOT part of Power Good tree of GPO1 pin and is ignored.
3 VTT_MSK R/W OTP-Programmable 0: VTT LDO PG is part of Power Good tree of GPO1 pin.
1: VTT LDO PG is NOT part of Power Good tree of GPO1 pin and is ignored.
0 LDOA3_MSK R/W OTP-Programmable 0: LDOA3 PG is part of Power Good tree of GPO1 pin.
1: LDOA3 PG is NOT part of Power Good tree of GPO1 pin and is ignored.

5.9.41 GPO4PG_CTRL1: GPO4 PG Control1 Register (offset = A6h) [reset = OTP-Programmable]

Figure 5-58 GPO4PG_CTRL1 Register
Bit 7 6 5 4 3 2 1 0
Bit Name LDOA2_MSK RESERVED BUCK6_MSK BUCK5_MSK BUCK4_MSK BUCK3_MSK BUCK2_MSK BUCK1_MSK
TPS650860 1 1 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-46 GPO4PG_CTRL1 Register Descriptions

Bit Field Type Reset Description
7 LDOA2_MSK R/W OTP-Programmable 0: LDOA2 PG is part of Power Good tree of GPO4 pin.
1: LDOA2 PG is NOT part of Power Good tree of GPO4 pin and is ignored.
5 BUCK6_MSK R/W OTP-Programmable 0: BUCK6 PG is part of Power Good tree of GPO4 pin.
1: BUCK6 PG is NOT part of Power Good tree of GPO4 pin and is ignored.
4 BUCK5_MSK R/W OTP-Programmable 0: BUCK5 PG is part of Power Good tree of GPO4 pin.
1: BUCK5 PG is NOT part of Power Good tree of GPO4 pin and is ignored.
3 BUCK4_MSK R/W OTP-Programmable 0: BUCK4 PG is part of Power Good tree of GPO4 pin.
1: BUCK4 PG is NOT part of Power Good tree of GPO4 pin and is ignored.
2 BUCK3_MSK R/W OTP-Programmable 0: BUCK3 PG is part of Power Good tree of GPO4 pin.
1: BUCK3 PG is NOT part of Power Good tree of GPO4 pin and is ignored.
1 BUCK2_MSK R/W OTP-Programmable 0: BUCK2 PG is part of Power Good tree of GPO4 pin.
1: BUCK2 PG is NOT part of Power Good tree of GPO4 pin and is ignored.
0 BUCK1_MSK R/W OTP-Programmable 0: BUCK1 PG is part of Power Good tree of GPO4 pin.
1: BUCK1 PG is NOT part of Power Good tree of GPO4 pin and is ignored.

5.9.42 GPO4PG_CTRL2: GPO4 PG Control2 Register (offset = A7h) [reset = OTP-Programmable]

Figure 5-59 GPO4PG_CTRL2 Register
Bit 7 6 5 4 3 2 1 0
Bit Name CTL5_MSK CTL4_MSK CTL2_MSK CTL1_MSK VTT_MSK RESERVED RESERVED LDOA3_MSK
TPS650860 1 1 0 0 1 1 1 1
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-47 GPO4PG_CTRL2 Register Descriptions

Bit Field Type Reset Description
7 CTL5_MSK R/W OTP-Programmable 0: CTL5 pin status is part of Power Good tree of GPO4 pin.
1: CTL5 pin status is NOT part of Power Good tree of GPO4 pin and is ignored.
6 CTL4_MSK R/W OTP-Programmable 0: CTL4 pin status is part of Power Good tree of GPO4 pin.
1: CTL4 pin status is NOT part of Power Good tree of GPO4 pin and is ignored.
5 CTL2_MSK R/W OTP-Programmable 0: CTL2 pin status is part of Power Good tree of GPO4 pin.
1: CTL2 pin status is NOT part of Power Good tree of GPO4 pin and is ignored.
4 CTL1_MSK R/W OTP-Programmable 0: CTL1 pin status is part of Power Good tree of GPO4 pin.
1: CTL1 pin status is NOT part of Power Good tree of GPO4 pin and is ignored.
3 VTT_MSK R/W OTP-Programmable 0: VTT LDO PG is part of Power Good tree of GPO4 pin.
1: VTT LDO PG is NOT part of Power Good tree of GPO4 pin and is ignored.
0 LDOA3_MSK R/W OTP-Programmable 0: LDOA3 PG is part of Power Good tree of GPO4 pin.
1: LDOA3 PG is NOT part of Power Good tree of GPO4 pin and is ignored.

5.9.43 GPO2PG_CTRL1: GPO2 PG Control1 Register (offset = A8h) [reset = OTP-Programmable]

Figure 5-60 GPO2PG_CTRL1 Register
Bit 7 6 5 4 3 2 1 0
Bit Name LDOA2_MSK RESERVED BUCK6_MSK BUCK5_MSK BUCK4_MSK BUCK3_MSK BUCK2_MSK BUCK1_MSK
TPS650860 1 1 0 1 1 1 1 1
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-48 GPO2PG_CTRL1 Register Descriptions

Bit Field Type Reset Description
7 LDOA2_MSK R/W OTP-Programmable 0: LDOA2 PG is part of Power Good tree of GPO2 pin.
1: LDOA2 PG is NOT part of Power Good tree of GPO1 pin and is ignored.
5 BUCK6_MSK R/W OTP-Programmable 0: BUCK6 PG is part of Power Good tree of GPO2 pin.
1: BUCK6 PG is NOT part of Power Good tree of GPO2 pin and is ignored.
4 BUCK5_MSK R/W OTP-Programmable 0: BUCK5 PG is part of Power Good tree of GPO2 pin.
1: BUCK5 PG is NOT part of Power Good tree of GPO2 pin and is ignored.
3 BUCK4_MSK R/W OTP-Programmable 0: BUCK4 PG is part of Power Good tree of GPO2 pin.
1: BUCK4 PG is NOT part of Power Good tree of GPO2 pin and is ignored.
2 BUCK3_MSK R/W OTP-Programmable 0: BUCK3 PG is part of Power Good tree of GPO2 pin.
1: BUCK3 PG is NOT part of Power Good tree of GPO2 pin and is ignored.
1 BUCK2_MSK R/W OTP-Programmable 0: BUCK2 PG is part of Power Good tree of GPO2 pin.
1: BUCK2 PG is NOT part of Power Good tree of GPO2 pin and is ignored.
0 BUCK1_MSK R/W OTP-Programmable 0: BUCK1 PG is part of Power Good tree of GPO2 pin.
1: BUCK1 PG is NOT part of Power Good tree of GPO2 pin and is ignored.

5.9.44 GPO2PG_CTRL2: GPO2 PG Control2 Register (offset = A9h) [reset = OTP-Programmable]

Figure 5-61 GPO2PG_CTRL2 Register
Bit 7 6 5 4 3 2 1 0
Bit Name CTL5_MSK CTL4_MSK CTL2_MSK CTL1_MSK VTT_MSK RESERVED RESERVED LDOA3_
MSK
TPS650860 1 1 0 1 1 1 1 1
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-49 GPO2PG_CTRL2 Register Descriptions

Bit Field Type Reset Description
7 CTL5_MSK R/W OTP-Programmable 0: CTL5 pin status is part of Power Good tree of GPO2 pin.
1: CTL5 pin status is NOT part of Power Good tree of GPO2 pin and is ignored.
6 CTL4_MSK R/W OTP-Programmable 0: CTL4 pin status is part of Power Good tree of GPO2 pin.
1: CTL4 pin status is NOT part of Power Good tree of GPO2 pin and is ignored.
5 CTL2_MSK R/W OTP-Programmable 0: CTL2 pin status is part of Power Good tree of GPO2 pin.
1: CTL2 pin status is NOT part of Power Good tree of GPO2 pin and is ignored.
4 CTL1_MSK R/W OTP-Programmable 0: CTL1 pin status is part of Power Good tree of GPO2 pin.
1: CTL1 pin status is NOT part of Power Good tree of GPO2 pin and is ignored.
3 VTT_MSK R/W OTP-Programmable 0: VTT LDO PG is part of Power Good tree of GPO2 pin.
1: VTT LDO PG is NOT part of Power Good tree of GPO2 pin and is ignored.
0 LDOA3_MSK R/W OTP-Programmable 0: LDOA3 PG is part of Power Good tree of GPO2 pin.
1: LDOA3 PG is NOT part of Power Good tree of GPO2 pin and is ignored.

5.9.45 GPO3PG_CTRL1: GPO3 PG Control1 Register (offset = AAh) [reset = OTP-Programmable]

Figure 5-62 GPO3PG_CTRL1 Register
Bit 7 6 5 4 3 2 1 0
Bit Name LDOA2
_MSK		 RESERVED BUCK6
_MSK		 BUCK5
_MSK		 BUCK4
_MSK		 BUCK3
_MSK		 BUCK2
_MSK		 BUCK1
_MSK
TPS650860 0 1 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-50 GPO3PG_CTRL1 Register Descriptions

Bit Field Type Reset Description
7 LDOA2_MSK R/W OTP-Programmable 0: LDOA2 PG is part of Power Good tree of GPO3 pin.
1: LDOA2 PG is NOT part of Power Good tree of GPO3 pin and is ignored.
5 BUCK6_MSK R/W OTP-Programmable 0: BUCK6 PG is part of Power Good tree of GPO3 pin.
1: BUCK6 PG is NOT part of Power Good tree of GPO3 pin and is ignored.
4 BUCK5_MSK R/W OTP-Programmable 0: BUCK5 PG is part of Power Good tree of GPO3 pin.
1: BUCK5 PG is NOT part of Power Good tree of GPO3 pin and is ignored.
3 BUCK4_MSK R/W OTP-Programmable 0: BUCK4 PG is part of Power Good tree of GPO3 pin.
1: BUCK4 PG is NOT part of Power Good tree of GPO3 pin and is ignored.
2 BUCK3_MSK R/W OTP-Programmable 0: BUCK3 PG is part of Power Good tree of GPO3 pin.
1: BUCK3 PG is NOT part of Power Good tree of GPO3 pin and is ignored.
1 BUCK2_MSK R/W OTP-Programmable 0: BUCK2 PG is part of Power Good tree of GPO3 pin.
1: BUCK2 PG is NOT part of Power Good tree of GPO3 pin and is ignored.
0 BUCK1_MSK R/W OTP-Programmable 0: BUCK1 PG is part of Power Good tree of GPO3 pin.
1: BUCK1 PG is NOT part of Power Good tree of GPO3 pin and is ignored.

5.9.46 GPO3PG_CTRL2: GPO3 PG Control2 Register (offset = ABh) [reset = OTP-Programmable]

Figure 5-63 GPO3PG_CTRL2 Register
Bit 7 6 5 4 3 2 1 0
Bit Name CTL5_MSK CTL4_MSK CTL2_MSK CTL1_MSK VTT_MSK RESERVED RESERVED LDOA3_MSK
TPS650860 1 0 0 0 1 1 1 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-51 GPO3PG_CTRL2 Register Descriptions

Bit Field Type Reset Description
7 CTL5_MSK R/W OTP-Programmable 0: CTL5 pin status is part of Power Good tree of GPO3 pin.
1: CTL5 pin status is NOT part of Power Good tree of GPO3 pin and is ignored.
6 CTL4_MSK R/W OTP-Programmable 0: CTL4 pin status is part of Power Good tree of GPO3 pin.
1: CTL4 pin status is NOT part of Power Good tree of GPO3 pin and is ignored.
5 CTL2_MSK R/W OTP-Programmable 0: CTL2 pin status is part of Power Good tree of GPO3 pin.
1: CTL2 pin status is NOT part of Power Good tree of GPO3 pin and is ignored.
4 CTL1_MSK R/W OTP-Programmable 0: CTL1 pin status is part of Power Good tree of GPO3 pin.
1: CTL1 pin status is NOT part of Power Good tree of GPO3 pin and is ignored.
3 VTT_MSK R/W OTP-Programmable 0: VTT LDO PG is part of Power Good tree of GPO3 pin.
1: VTT LDO PG is NOT part of Power Good tree of GPO3 pin and is ignored.
0 LDOA3_MSK R/W OTP-Programmable 0: LDOA3 PG is part of Power Good tree of GPO3 pin.
1: LDOA3 PG is NOT part of Power Good tree of GPO3 pin and is ignored.

5.9.47 MISCSYSPG Register (offset = ACh) [reset = OTP-Programmable]

Figure 5-64 MISCSYSPG Register
Bit 7 6 5 4 3 2 1 0
Bit Name GPO1_
CTL3_MSK		 GPO1_
CTL6_MSK		 GPO4_
CTL3_MSK		 GPO4_
CTL6_MSK		 GPO2_
CTL3_MSK		 GPO2_
CTL6_MSK		 GPO3_
CTL3_MSK		 GPO3_
CTL6_MSK
TPS650860 1 1 1 1 1 1 1 1
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-52 MISCSYSPG Register Descriptions

Bit Field Type Reset Description
7 GPO1_CTL3_MSK R/W OTP-Programmable 0: CTL3 pin status is part of Power Good tree of GPO1 pin.
1: CTL3 pin status is NOT part of Power Good tree of GPO1 pin.
6 GPO1_CTL6_MSK R/W OTP-Programmable 0: CTL6 pin status is part of Power Good tree of GPO1 pin.
1: CTL6 pin status is NOT part of Power Good tree of GPO1 pin.
5 GPO4_CTL3_MSK R/W OTP-Programmable 0: CTL3 pin status is part of Power Good tree of GPO4 pin.
1: CTL3 pin status is NOT part of Power Good tree of GPO4 pin.
4 GPO4_CTL6_MSK R/W OTP-Programmable 0: CTL6 pin status is part of Power Good tree of GPO4 pin.
1: CTL6 pin status is NOT part of Power Good tree of GPO4 pin.
3 GPO2_CTL3_MSK R/W OTP-Programmable 0: CTL3 pin status is part of Power Good tree of GPO2 pin.
1: CTL3 pin status is NOT part of Power Good tree of GPO2 pin.
2 GPO2_CTL6_MSK R/W OTP-Programmable 0: CTL6 pin status is part of Power Good tree of GPO2 pin.
1: CTL6 pin status is NOT part of Power Good tree of GPO2 pin.
1 GPO3_CTL3_MSK R/W OTP-Programmable 0: CTL3 pin status is part of Power Good tree of GPO3 pin.
1: CTL3 pin status is NOT part of Power Good tree of GPO13pin.
0 GPO3_CTL6_MSK R/W OTP-Programmable 0: CTL6 pin status is part of Power Good tree of GPO3 pin.
1: CTL6 pin status is NOT part of Power Good tree of GPO3 pin.

5.9.48 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = OTP-Programmable]

Figure 5-65 LDOA1CTRL Register
Bit 7 6 5 4 3 2 1 0
Bit Name LDOA1_
DISCHG[1]		 LDOA1_
DISCHG[0]		 LDOA1_SDWN
_CONFIG		 LDOA1_
VID[3]		 LDOA1_
VID[2]		 LDOA1_
VID[1]		 LDOA1_
VID[0]		 LDOA1_
EN
TPS650860 0 1 1 1 1 1 0 1
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-53 LDOA1CTRL Register Descriptions

Bit Field Type Reset Description
7-6 LDOA1_DISCHG[1:0] R/W OTP-Programmable LDOA1 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
5 LDOA1_SDWN_CONFIG R/W OTP-Programmable Control for Disabling LDOA1 during Emergency Shutdown
0: LDOA1 will turn off during Emergency Shutdown for factory-programmable duration of 1 ms, 5 ms, 10 ms, or 100 ms.
1: LDOA1 is controlled by LDOA1_EN bit only.
4-1 LDOA1_VID[3:0] R/W OTP-Programmable This field sets the LDOA1 regulator output regulation voltage.
See Table 5-4 for VOUT options.
0 LDOA1_EN R/W OTP-Programmable LDOA1 Enable Bit.
0: Disable.
1: Enable.

5.9.49 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0000 0000]

Figure 5-66 PG_STATUS1 Register
Bit 7 6 5 4 3 2 1 0
Bit Name LDOA2_
PGOOD		 RESERVED BUCK6_
PGOOD		 BUCK5_
PGOOD		 BUCK4_
PGOOD		 BUCK3_
PGOOD		 BUCK2_
PGOOD		 BUCK1_
PGOOD
TPS650860 0 0 0 0 0 0 0 0
Access R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-54 PG_STATUS1 Register Descriptions

Bit Field Type Reset Description
7 LDOA2_PGOOD R 0 LDOA2 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
5 BUCK6_PGOOD R 0 BUCK6 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
4 BUCK5_PGOOD R 0 BUCK5 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
3 BUCK4_PGOOD R 0 BUCK4 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
2 BUCK3_PGOOD R 0 BUCK3 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
1 BUCK2_PGOOD R 0 BUCK2 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
0 BUCK1_PGOOD R 0 BUCK1 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.

5.9.50 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0000 0000]

Figure 5-67 PG_STATUS2 Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED LDO5
_PGOOD		 LDOA1
_PGOOD		 VTT
_PGOOD		 RESERVED RESERVED LDOA3
_PGOOD
TPS650860 0 0 0 0 0 0 0 0
Access R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-55 PG_STATUS2 Register Descriptions

Bit Field Type Reset Description
5 LDO5_PGOOD R 0 LDO5 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
4 LDOA1_PGOOD R 0 LDOA1 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
3 VTT_PGOOD R 0 VTT LDO Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
0 LDOA3_PGOOD R 0 LDOA3 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.

5.9.51 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0000 0000]

Figure 5-68 PWR_FAULT_STATUS1 Register
Bit 7 6 5 4 3 2 1 0
Bit Name LDOA2_
PWRFLT		 RESERVED BUCK6_
PWRFLT		 BUCK5_
PWRFLT		 BUCK4_
PWRFLT		 BUCK3_
PWRFLT		 BUCK2_
PWRFLT		 BUCK1_
PWRFLT
TPS650860 0 0 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-56 PWR_FAULT_STATUS1 Register Descriptions

Bit Field Type Reset Description
7 LDOA2_PWRFLT R 0 This fields indicates that LDOA2 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
5 BUCK6_PWRFLT R 0 This fields indicates that BUCK6 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
4 BUCK5_PWRFLT R 0 This fields indicates that BUCK5 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
3 BUCK4_PWRFLT R 0 This fields indicates that BUCK4 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
2 BUCK3_PWRFLT R 0 This fields indicates that BUCK3 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
1 BUCK2_PWRFLT R 0 This fields indicates that BUCK2 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
0 BUCK1_PWRFLT R 0 This fields indicates that BUCK1 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.

5.9.52 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0000 0000]

Figure 5-69 PWR_FAULT_STATUS2 Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED RESERVED LDOA1_
PWRFLT		 VTT_
PWRFLT		 RESERVED RESERVED LDOA3_
PWRFLT
TPS650860 0 0 0 0 0 0 0 0
Access R R R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-57 PWR_FAULT_STATUS2 Register Descriptions

Bit Field Type Reset Description
4 LDOA1_PWRFLT R/W 0 This fields indicates that LDOA1 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
3 VTT_PWRFLT R/W 0 This fields indicates that VTT LDO has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
0 LDOA3_PWRFLT R/W 0 This fields indicates that LDOA3 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.

5.9.53 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0000 0000]

Asserted when an internal temperature sensor detects rise of die temperature above the CRITICAL temperature threshold (TCRIT). There are 5 temperature sensors across the die.

Figure 5-70 TEMPCRIT Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED RESERVED DIE_CRIT VTT_CRIT Top-Right
_CRIT		 Top-Left
_CRIT		 Bottom-Right
_CRIT
TPS650860 0 0 0 0 0 0 0 0
Access R R R R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-58 TEMPCRIT Register Descriptions

Bit Field Type Reset Description
4 DIE_CRIT R/W 0 Temperature of rest of die has exceeded TCRIT.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
3 VTT_CRIT R/W 0 Temperature of VTT LDO has exceeded TCRIT.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
2 Top-Right_CRIT R/W 0 Temperature of die Top-Right has exceeded TCRIT. Top-Right corner of die from top view given pin1 is in Top-Left corner.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
1 Top-Left_CRIT R/W 0 Temperature of die Top-Left has exceeded TCRIT.Top-Left corner of die from top view given pin1 is in Top-Left corner.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
0 Bottom-Right_CRIT R/W 0 Temperature of die Bottom-Right has exceeded TCRIT. Bottom-Right corner of die from top view given pin1 is in Top-Left corner.
0: Not asserted.
1: Asserted. The host to write 1 to clear.

5.9.54 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]

Asserted when an internal temperature sensor detects rise of die temperature above the HOT temperature threshold (THOT). There are 5 temperature sensors across the die.

Figure 5-71 TEMPHOT Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED RESERVED DIE_HOT VTT_HOT Top-Right
_HOT		 Top-Left
_HOT		 Bottom-Right
_HOT
TPS650860 0 0 0 0 0 0 0 0
Access R R R R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-59 TEMPHOT Register Descriptions

Bit Field Type Reset Description
4 DIE_HOT R/W 0 Temperature of rest of die has exceeded THOT.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
3 VTT_HOT R/W 0 Temperature of VTT LDO has exceeded THOT.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
2 Top-Right_HOT R/W 0 Temperature of Top-Right has exceeded THOT. Top-Right corner of die from top view given pin1 is in Top-Left corner.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
1 Top-Left_HOT R/W 0 Temperature of Top-Left has exceeded THOT. Top-Left corner of die from top view given pin1 is in Top-Left corner.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
0 Bottom-Right_HOT R/W 0 Temperature of Bottom-Right has exceeded THOT. Bottom-Right corner of die from top view given pin1 is in Top-Left corner.
0: Not asserted.
1: Asserted. The host to write 1 to clear.

5.9.55 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0000 0000]

Asserted when overcurrent condition is detected from a LSD FET.

Figure 5-72 OC_STATUS Register
Bit 7 6 5 4 3 2 1 0
Bit Name RESERVED RESERVED RESERVED RESERVED RESERVED BUCK6
_OC		 BUCK2
_OC		 BUCK1
_OC
TPS650860 0 0 0 0 0 0 0 0
Access R R R R R R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-60 OC_STATUS Register Descriptions

Bit Field Type Reset Description
2 BUCK6_OC R/W 0 BUCK6 LSD FET overcurrent has been detected.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
1 BUCK2_OC R/W 0 BUCK2 LSD FET overcurrent has been detected.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
0 BUCK1_OC R/W 0 BUCK1 LSD FET overcurrent has been detected.
0: Not asserted.
1: Asserted. The host to write 1 to clear.