JAJSGZ1E September   2015  – October 2024 TPS65094

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
    1. 4.1 OTP Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Total Current Consumption
    6. 6.6  Electrical Characteristics: Reference and Monitoring System
    7. 6.7  Electrical Characteristics: Buck Controllers
    8. 6.8  Electrical Characteristics: Synchronous Buck Converters
    9. 6.9  Electrical Characteristics: LDOs
    10. 6.10 Electrical Characteristics: Load Switches
    11. 6.11 Digital Signals: I2C Interface
    12. 6.12 Digital Input Signals (LDOLS_EN, SWA1_EN, THERMTRIPB, PMICEN, SLP_S3B, SLP_S4B, SLP_S0B)
    13. 6.13 Digital Output Signals (IRQB, RSMRSTB, PCH_PWROK, PROCHOT)
    14. 6.14 Timing Requirements
    15. 6.15 Switching Characteristics
    16. 6.16 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Good (PGOOD)
      2. 7.3.2 Register Reset Conditions
      3. 7.3.3 SMPS Voltage Regulators
        1. 7.3.3.1 Controller Overview
        2. 7.3.3.2 Converter Overview
        3. 7.3.3.3 DVS
        4. 7.3.3.4 Current Limit
      4. 7.3.4 LDOs and Load Switches
        1. 7.3.4.1 VTT LDO
        2. 7.3.4.2 LDOA1–LDOA3
        3. 7.3.4.3 Load Switches
      5. 7.3.5 Power Sequencing and VR Control
        1. 7.3.5.1 Cold Boot
        2. 7.3.5.2 Cold OFF
        3. 7.3.5.3 Connected Standby Entry and Exit
        4. 7.3.5.4 S0 to S3 Entry and Exit
        5. 7.3.5.5 S0 to S4/5 Entry and Exit
        6. 7.3.5.6 Emergency Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 F/S-Mode Protocol
    6. 7.6 Register Maps
      1. 7.6.1  55
      2. 7.6.2  VENDORID: PMIC Vendor ID Register (offset = 00h) [reset = 0010 0010]
      3. 7.6.3  DEVICEID: PMIC Device and Revision ID Register (offset = 01h) [reset = OTP Dependent]
      4. 7.6.4  IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
      5. 7.6.5  IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
      6. 7.6.6  PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
      7. 7.6.7  OFFONSRC: PMIC Power Transition Event Register (offset = 05h) [reset = 0000 0000]
      8. 7.6.8  BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = 0011 1000]
      9. 7.6.9  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 0000 0000]
      10. 7.6.10 BUCK3CTRL: BUCK3 Control Register (offset = 23h) [reset = 0001 0001]
      11. 7.6.11 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = OTP Dependent]
      12. 7.6.12 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = OTP Dependent]
      13. 7.6.13 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = 0011 1101]
      14. 7.6.14 DISCHCNT1: Discharge Control1 Register (offset = 40h) [reset = 0101 0101]
      15. 7.6.15 DISCHCNT2: Discharge Control2 Register (offset = 41h) [reset = 0101 0101]
      16. 7.6.16 DISCHCNT3: Discharge Control3 Register (offset = 42h) [reset = 0000 0101]
      17. 7.6.17 POK_DELAY: PCH_PWROK Delay Register (offset = 43h) [reset = 0000 0111]
      18. 7.6.18 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
      19. 7.6.19 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 0010 1111]
      20. 7.6.20 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 0100 1011]
      21. 7.6.21 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = OTP Dependent]
      22. 7.6.22 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = OTP Dependent]
      23. 7.6.23 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = OTP Dependent]
      24. 7.6.24 VR_CTRL1: BUCK1-3 Control Register (offset = 9Ch) [reset = OTP Dependent]
      25. 7.6.25 VR_CTRL2: VR Enable Register (offset = 9Eh) [reset = 0000 0000]
      26. 7.6.26 VR_CTRL3: VR Enable/Disable Register (offset = 9Fh) [reset = OTP Dependent]
      27. 7.6.27 GPO_CTRL: GPO Control Register (offset = A1h) [reset = 0010 0000]
      28. 7.6.28 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = 1100 0000]
      29. 7.6.29 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 0011 0111]
      30. 7.6.30 DISCHCNT4: Discharge Control4 Register (offset = ADh) [reset = 0110 0001]
      31. 7.6.31 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = OTP Dependent]
      32. 7.6.32 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0000 0000]
      33. 7.6.33 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0000 0000]
        1. 7.6.33.1 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0000 0000]
        2. 7.6.33.2 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0000 0000]
      34. 7.6.34 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
  9. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Controller Design Procedure
          1. 8.1.2.1.1 Selecting the Output Capacitors
          2. 8.1.2.1.2 Selecting the Inductor
          3. 8.1.2.1.3 Selecting the FETs
          4. 8.1.2.1.4 Bootstrap Capacitor
          5. 8.1.2.1.5 Selecting the Input Capacitors
            1. 8.1.2.1.5.1 Setting the Current Limit
        2. 8.1.2.2 Converter Design Procedure
          1. 8.1.2.2.1 Selecting the Inductor
          2. 8.1.2.2.2 Selecting the Output Capacitors
          3. 8.1.2.2.3 Selecting the Input Capacitors
        3. 8.1.2.3 LDO Design Procedure
      3. 8.1.3 Application Curves
    2. 8.2 Specific Application for TPS650944
    3. 8.3 Dos and Don'ts
    4.     Power Supply Recommendations
    5. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Electrical Characteristics: Buck Controllers

over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
BUCK1
VINPower input voltage for external HSD FET5.61321V
VOUTDC output voltageStep size10mV
BUCK1_VID[6:0] = 00000000V
BUCK1_VID[6:0] = 00000010.5
BUCK1_VID[6:0] = 00000100.51
⋮⋮
BUCK1_VID[6:0] = 0110011 (default)1.00
⋮⋮
BUCK1_VID[6:0] = 11101011.66
BUCK1_VID[6:0] = 1110110–11111111.67
DC output voltage accuracyVOUT ≥ 1 V, IOUT = 100 mA to 5 A–2%2%
VOUT = 0.75 V, IOUT = 100 mA to 2.1 A–2.5%2.5%
VOUT ≤ 0.6 V, IOUT = 10 mA–3.5%3.5%
Total output voltage accuracy (DC + ripple) in DCMIOUT = 10 mA, VOUT ≤ 0.785 V, VSYS = 13 V–2040mV
IOUT = 10 mA, VOUT ≤ 0.785 V, VSYS = 21 V–2055
SR(VOUT)Output DVS slew rate2.53.125mV/µs
ILIM_LSDLow-side output valley current limit accuracy (programmed by external resistor RLIM)See Section 7.3.3.4, Current Limit, for details.–15%15%
VTH_ZCLow-side current zero crossing detection threshold–1111mV
ILIMREFSource current out of ILIM1 pinT = 25°C455055µA
VLIMVoltage at ILIM1 pinVLIM = RLIM × ILIMREF0.22.25V
ΔVOUT/ΔVINLine regulationVOUT ≥ 1 V, IOUT = 5 A–0.5%0.5%
ΔVOUT/ΔIOUTLoad regulationVIN = 13 V, VOUT ≥ 1 V,
IOUT = 0 A to 5 A,
referenced to VOUT at IOUT = 5 A		0%1%
ΔVOUT_TR(1)Load transient regulationDC + AC at sense point, VIN = 13 V,
VOUT = 1.00 V,
IOUT = 1.5 A to 5 A and 5 A to 1.5 A with 1 µs of tr and tf		–5050mV
DC + AC at sense point, VIN = 13 V,
VOUT = 0.75 V,
IOUT = 0.3 A to 1.5 A and 1.5 A to 0.3 A with 1 µs of tr and tf
VTH_PGPower Good deassertion threshold in percentage of target VOUTVOUT rising108%
VOUT falling92%
VTH_HYS_PGPower Good reassertion hysteresis entering back into VTH_PGVOUT rising or falling3%
COUTExternal output capacitanceRecommended amount to meet transient specification180220µF
LSWExternal output inductance0.3760.470.564µH
RDSON_DRVHDriver DRVH resistanceSource, IDRVH = –50 mA3Ω
Sink, IDRVH = 50 mA2
RDSON_DRVLDriver DRVL resistanceSource, IDRVL = –50 mA3Ω
Sink, IDRVL = 50 mA0.4
RDISOutput auto-discharge resistanceBUCK1_DIS[1:0] = 01100Ω
BUCK1_DIS[1:0] = 10200
BUCK1_DIS[1:0] = 11500
CBOOTBootstrap capacitance100nF
RON_BOOTBootstrap switch ON resistance20Ω
BUCK2
VINPower input voltage for external HSD FET5.61321V
VOUTDC output voltage Step size10mV
BUCK2_VID[6:0] = 0000000 (default)0V
BUCK2_VID[6:0] = 00000010.5
BUCK2_VID[6:0] = 00000100.51
⋮⋮
BUCK2_VID[6:0] = 11101011.66
BUCK2_VID[6:0] = 1110110–11111111.67
DC output voltage accuracyVOUT ≥ 1 V, IOUT = 100 mA to 21 A–2%2%
VOUT = 0.75 V, IOUT = 100 mA to 6.3 A–2.5%2.5%
VOUT ≤ 0.6 V, IOUT = 10 mA–3.5%3.5%
Total output voltage accuracy (DC + ripple) in DCMIOUT = 10 mA, VOUT ≤ 0.765 V–2040mV
SR(VOUT)Output DVS slew rate2.53.125mV/µs
ILIM_LSDLow-side output valley current limit accuracy (programmed by external resistor RLIM)See Section 7.3.3.4, Current Limit, for details.–15%15%
VTH_ZCLow-side current zero crossing detection threshold–1111mV
ILIMREFSource current out of ILIM2 pinT = 25°C455055µA
VLIMVoltage at ILIM2 pinVLIM = RLIM × ILIMREF0.22.25V
ΔVOUT/ΔVINLine regulationVOUT ≥ 1 V, IOUT = 21 A–0.5%0.5%
ΔVOUT/ΔIOUTLoad regulationVIN = 13 V, 1 V ≤ VOUT ≤ 1.3 V,
IOUT = 0 A to 21 A,
referenced to VOUT at IOUT = 21 A		0%1%
ΔVOUT_TR(1)Load transient regulationDC + AC at sense point, VIN = 13 V, VOUT = 1 V,
IOUT = 1 A to 21 A and 21 A to 1 A with 1 µs of tr and tf		–16030(2)mV
DC + AC at sense point, VIN = 13 V,
VOUT = 0.75 V, IOUT = 1 A to 3.3 A and 3.3 A to
1 A with 1 µs of tr and tf		–5050(2)
VTH_PGPower Good deassertion threshold in percentage of target VOUTVOUT rising108%
VOUT falling92%
VTH_HYS_PGPower Good reassertion hysteresis entering back into VTH_PGVOUT rising or falling3%
LSWExternal output inductance0.1760.220.264µH
COUTExternal output capacitanceRecommended amount to meet transient specification440550µF
RDSON_DRVHDriver DRVH resistanceSource, IDRVH = –50 mA3Ω
Sink, IDRVH = 50 mA2
RDSON_DRVLDriver DRVL resistanceSource, IDRVL = –50 mA3Ω
Sink, IDRVL = 50 mA0.4
RDISOutput auto-discharge resistanceBUCK2_DIS[1:0] = 01100Ω
BUCK2_DIS[1:0] = 10200
BUCK2_DIS[1:0] = 11500
CBOOTBootstrap capacitance100nF
RON_BOOTBootstrap switch ON resistance20Ω
BUCK6
VINPower input voltage for external HSD FET5.61321V
VOUTDC output voltageStep size10mV
BUCK6_VID[6:0] = 00000000V
BUCK6_VID[6:0] = 00000010.5
BUCK6_VID[6:0] = 00000100.51
⋮⋮
BUCK6_VID[6:0] = 0111101 (TPS650940 and TPS650944 default)1.1
⋮⋮
BUCK6_VID[6:0] = 1000111 (TPS650941 default)1.2
⋮⋮
BUCK6_VID[6:0] = 1010110 (TPS650942 default)1.35
⋮⋮
BUCK6_VID[6:0] = 11101011.66
BUCK6_VID[6:0] = 1110110–11111111.67
DC output voltage accuracyVOUT ≥ 1 V, IOUT = 100 mA to 7 A–2%2%
ILIM_LSDLow-side output valley current limit accuracy (programmed by external resistor RLIM)See Section 7.3.3.4, Current Limit, for details.–15%15%
VTH_ZCLow-side current zero crossing detection threshold–1111mV
ILIMREFSource current out of ILIM6 pinT = 25°C455055µA
VLIMVoltage at ILIM6 pinVLIM = RLIM × ILIMREF0.22.25V
ΔVOUT/ΔVINLine regulationVOUT ≥ 1 V, IOUT = 7 A–0.5%0.5%
ΔVOUT/ΔIOUTLoad regulationVIN = 13 V, VOUT ≥ 1 V, IOUT = 0 A to 7 A, referenced to VOUT at IOUT = 7 A0%1%
ΔVOUT_TR Load transient regulationDC + AC at sense point, VIN = 13 V,
VOUT = 1.35 V, IOUT = 2.1 A to 7 A and 7 A to 2.1 A with 1.96 µs of tr and tf (2.5 A/µs)		–5%5%
VTH_PGPower Good deassertion threshold in percentage of target VOUTVOUT rising108%
VOUT falling92%
VTH_HYS_PGPower Good reassertion hysteresis entering back into VTH_PGVOUT rising or falling3%
LSWExternal output inductance0.3760.470.564µH
COUTExternal output capacitanceRecommended amount to meet transient specification150220µF
RDSON_DRVHDriver DRVH resistanceSource, IDRVH = –50 mA3Ω
Sink, IDRVH = 50 mA2
RDSON_DRVLDriver DRVL resistanceSource, IDRVL = –50 mA3Ω
Sink, IDRVL = 50 mA0.4
RDISOutput auto-discharge resistanceBUCK6_DIS[1:0] = 01100Ω
BUCK6_DIS[1:0] = 10200
BUCK6_DIS[1:0] = 11500
CBOOTBootstrap capacitance100nF
RON_BOOTBootstrap switch ON resistance20Ω
(1) Frequency of transient load current ranges from 0 to 1 MHz with duty cycle of 50%. For cases where duty cycle and frequency are limited by tr and tf, the highest frequency is set by 1 / (tr + tf), where tr is rise time (0% to 100%) and tf is fall time (100% to 0%).
(2) Additional overshoot of up to 100 mV is allowed as long as it lasts less than 50 µs.