JAJSGZ1E September   2015  – October 2024 TPS65094

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
    1. 4.1 OTP Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Total Current Consumption
    6. 6.6  Electrical Characteristics: Reference and Monitoring System
    7. 6.7  Electrical Characteristics: Buck Controllers
    8. 6.8  Electrical Characteristics: Synchronous Buck Converters
    9. 6.9  Electrical Characteristics: LDOs
    10. 6.10 Electrical Characteristics: Load Switches
    11. 6.11 Digital Signals: I2C Interface
    12. 6.12 Digital Input Signals (LDOLS_EN, SWA1_EN, THERMTRIPB, PMICEN, SLP_S3B, SLP_S4B, SLP_S0B)
    13. 6.13 Digital Output Signals (IRQB, RSMRSTB, PCH_PWROK, PROCHOT)
    14. 6.14 Timing Requirements
    15. 6.15 Switching Characteristics
    16. 6.16 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Good (PGOOD)
      2. 7.3.2 Register Reset Conditions
      3. 7.3.3 SMPS Voltage Regulators
        1. 7.3.3.1 Controller Overview
        2. 7.3.3.2 Converter Overview
        3. 7.3.3.3 DVS
        4. 7.3.3.4 Current Limit
      4. 7.3.4 LDOs and Load Switches
        1. 7.3.4.1 VTT LDO
        2. 7.3.4.2 LDOA1–LDOA3
        3. 7.3.4.3 Load Switches
      5. 7.3.5 Power Sequencing and VR Control
        1. 7.3.5.1 Cold Boot
        2. 7.3.5.2 Cold OFF
        3. 7.3.5.3 Connected Standby Entry and Exit
        4. 7.3.5.4 S0 to S3 Entry and Exit
        5. 7.3.5.5 S0 to S4/5 Entry and Exit
        6. 7.3.5.6 Emergency Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 F/S-Mode Protocol
    6. 7.6 Register Maps
      1. 7.6.1  55
      2. 7.6.2  VENDORID: PMIC Vendor ID Register (offset = 00h) [reset = 0010 0010]
      3. 7.6.3  DEVICEID: PMIC Device and Revision ID Register (offset = 01h) [reset = OTP Dependent]
      4. 7.6.4  IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
      5. 7.6.5  IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
      6. 7.6.6  PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
      7. 7.6.7  OFFONSRC: PMIC Power Transition Event Register (offset = 05h) [reset = 0000 0000]
      8. 7.6.8  BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = 0011 1000]
      9. 7.6.9  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 0000 0000]
      10. 7.6.10 BUCK3CTRL: BUCK3 Control Register (offset = 23h) [reset = 0001 0001]
      11. 7.6.11 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = OTP Dependent]
      12. 7.6.12 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = OTP Dependent]
      13. 7.6.13 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = 0011 1101]
      14. 7.6.14 DISCHCNT1: Discharge Control1 Register (offset = 40h) [reset = 0101 0101]
      15. 7.6.15 DISCHCNT2: Discharge Control2 Register (offset = 41h) [reset = 0101 0101]
      16. 7.6.16 DISCHCNT3: Discharge Control3 Register (offset = 42h) [reset = 0000 0101]
      17. 7.6.17 POK_DELAY: PCH_PWROK Delay Register (offset = 43h) [reset = 0000 0111]
      18. 7.6.18 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
      19. 7.6.19 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 0010 1111]
      20. 7.6.20 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 0100 1011]
      21. 7.6.21 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = OTP Dependent]
      22. 7.6.22 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = OTP Dependent]
      23. 7.6.23 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = OTP Dependent]
      24. 7.6.24 VR_CTRL1: BUCK1-3 Control Register (offset = 9Ch) [reset = OTP Dependent]
      25. 7.6.25 VR_CTRL2: VR Enable Register (offset = 9Eh) [reset = 0000 0000]
      26. 7.6.26 VR_CTRL3: VR Enable/Disable Register (offset = 9Fh) [reset = OTP Dependent]
      27. 7.6.27 GPO_CTRL: GPO Control Register (offset = A1h) [reset = 0010 0000]
      28. 7.6.28 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = 1100 0000]
      29. 7.6.29 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 0011 0111]
      30. 7.6.30 DISCHCNT4: Discharge Control4 Register (offset = ADh) [reset = 0110 0001]
      31. 7.6.31 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = OTP Dependent]
      32. 7.6.32 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0000 0000]
      33. 7.6.33 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0000 0000]
        1. 7.6.33.1 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0000 0000]
        2. 7.6.33.2 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0000 0000]
      34. 7.6.34 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
  9. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Controller Design Procedure
          1. 8.1.2.1.1 Selecting the Output Capacitors
          2. 8.1.2.1.2 Selecting the Inductor
          3. 8.1.2.1.3 Selecting the FETs
          4. 8.1.2.1.4 Bootstrap Capacitor
          5. 8.1.2.1.5 Selecting the Input Capacitors
            1. 8.1.2.1.5.1 Setting the Current Limit
        2. 8.1.2.2 Converter Design Procedure
          1. 8.1.2.2.1 Selecting the Inductor
          2. 8.1.2.2.2 Selecting the Output Capacitors
          3. 8.1.2.2.3 Selecting the Input Capacitors
        3. 8.1.2.3 LDO Design Procedure
      3. 8.1.3 Application Curves
    2. 8.2 Specific Application for TPS650944
    3. 8.3 Dos and Don'ts
    4.     Power Supply Recommendations
    5. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9 Electrical Characteristics: LDOs

over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LDOA1
VIN Input voltage 4.5 5 5.5 V
VOUT DC output voltage IOUT = 10 mA, LDOA1_SEL[3:0] = 0000 1.35 V
LDOA1_SEL[3:0] = 0001 1.5
LDOA1_SEL[3:0] = 0010 1.6
LDOA1_SEL[3:0] = 0011 1.7
LDOA1_SEL[3:0] = 0100 (TPS650944 default) 1.8
LDOA1_SEL[3:0] = 0101 1.9
LDOA1_SEL[3:0] = 0110 2
LDOA1_SEL[3:0] = 0111 2.1
LDOA1_SEL[3:0] = 1000 2.3
LDOA1_SEL[3:0] = 1001 2.4
LDOA1_SEL[3:0] = 1010 2.5
LDOA1_SEL[3:0] = 1011 2.7
LDOA1_SEL[3:0] = 1100 2.85
LDOA1_SEL[3:0] = 1101 3
LDOA1_SEL[3:0] = 1110 (TPS650940, TPS650941, and TPS650942 default) 3.3
VOUT Accuracy IOUT = 0 to 200 mA –2% 2%
IOUT DC output current 200 mA
ΔVOUT/ΔVIN Line regulation IOUT = 40 mA –0.5% 0.5%
ΔVOUT/ΔIOUT Load regulation IOUT = 10 mA to 200 mA –2% 2%
IOCP Overcurrent protection VIN = 5 V, Measured with output shorted to ground 500 mA
VTH_PG Power Good deassertion threshold in percentage of target VOUT VOUT rising 108%
VOUT falling 92%
VTH_HYS_PG Power Good reassertion hysteresis entering back into VTH_PG VOUT rising or falling 3%
IQ Quiescent current IOUT = 0 A 23 µA
COUT External output capacitance 2.7 4.7 10 µF
ESR 100 mΩ
RDIS Output auto-discharge resistance LDOA1_DIS[1:0] = 01 100 Ω
LDOA1_DIS[1:0] = 10 190
LDOA1_DIS[1:0] = 11 450
LDOA2
VIN Power input voltage VOUT + VDROP(1) 1.8 1.98 V
VOUT DC output voltage in normal operating mode LDOA2_VID[3:0] = 0000 (TPS650944 default) 0.7 V
LDOA2_VID[3:0] = 0001 0.75
LDOA2_VID[3:0] = 0010 0.8
LDOA2_VID[3:0] = 0011 0.85
LDOA2_VID[3:0] = 0100 0.9
LDOA2_VID[3:0] = 0101 0.95
LDOA2_VID[3:0] = 0110 1
LDOA2_VID[3:0] = 0111 1.05
LDOA2_VID[3:0] = 1000 1.1
LDOA2_VID[3:0] = 1001 1.15
LDOA2_VID[3:0] = 1010 (TPS650940, TPS650941, and TPS650942 default) 1.2
LDOA2_VID[3:0] = 1011 1.25
LDOA2_VID[3:0] = 1100 1.3
LDOA2_VID[3:0] = 1101 1.35
LDOA2_VID[3:0] = 1110 1.4
LDOA2_VID[3:0] = 1111 1.5
VOUT DC output voltage accuracy IOUT = 0 to 600 mA –2% 3%
IOUT DC output current 600 mA
VDROP Dropout voltage VOUT = 0.99 × VOUT_NOM,
IOUT = 600 mA		 350 mV
ΔVOUT/ΔVIN Line regulation IOUT = 300 mA –0.5% 0.5%
ΔVOUT/ΔIOUT Load regulation IOUT = 10 mA to 600 mA –2% 2%
IOCP Overcurrent protection Measured with output shorted to ground 0.65 1.25 A
VTH_PG Power Good assertion threshold in percentage of target VOUT VOUT rising 108%
VOUT falling 92%
VTH_HYS_PG Power Good deassertion hysteresis VOUT falling 3%
IQ Quiescent current IOUT = 0 A 20 µA
PSRR Power supply rejection ratio f = 1 kHz, VIN = 1.8 V, VOUT = 1.2 V,
IOUT = 300 mA,
COUT = 2.2 µF to 4.7 µF		 48 dB
f = 10 kHz, VIN = 1.8 V, VOUT = 1.2 V,
IOUT = 300 mA,
COUT = 2.2 µF to 4.7 µF		 30 dB
COUT External output capacitance 2.2 4.7 10 µF
ESR 100 mΩ
RDIS Output auto-discharge resistance LDOA2_DIS[1:0] = 01 80 Ω
LDOA2_DIS[1:0] = 10 180
LDOA2_DIS[1:0] = 11 475
LDOA3
VIN Power input voltage VOUT + VDROP(1) 1.8 1.98 V
VOUT DC output voltage in normal operating mode LDOA3_VID[3:0] = 0000 (TPS650944 default) 0.7 V
LDOA3_VID[3:0] = 0001 0.75
LDOA3_VID[3:0] = 0010 0.8
LDOA3_VID[3:0] = 0011 0.85
LDOA3_VID[3:0] = 0100 0.9
LDOA3_VID[3:0] = 0101 0.95
LDOA3_VID[3:0] = 0110 1
LDOA3_VID[3:0] = 0111 1.05
LDOA3_VID[3:0] = 1000 1.1
LDOA3_VID[3:0] = 1001 1.15
LDOA3_VID[3:0] = 1010 1.2
LDOA3_VID[3:0] = 1011 (TPS650940, TPS650941, and TPS650942 default) 1.25
LDOA3_VID[3:0] = 1100 1.3
LDOA3_VID[3:0] = 1101 1.35
LDOA3_VID[1:0] = 1110 1.4
LDOA3_VID[1:0] = 1111 1.5
VOUT DC output voltage accuracy IOUT = 0 to 600 mA –2% 3%
IOUT DC output current 600 mA
IOCP Overcurrent protection Measured with output shorted to ground 0.65 1.25 A
VDROP Dropout voltage VOUT = 0.99 × VOUT_NOM,
IOUT = 600 mA		 350 mV
ΔVOUT/ΔVIN Line regulation IOUT = 300 mA –0.5% 0.5%
ΔVOUT/ΔIOUT Load regulation IOUT = 10 mA to 600 mA –2% 2%
VTH_PG Power Good assertion threshold in percentage of target VOUT VOUT rising 108%
VOUT falling 92%
VTH_HYS_PG Power Good deassertion hysteresis VOUT falling 3%
IQ Quiescent current IOUT = 0 A 20 µA
PSRR Power supply rejection ratio f = 1 kHz, VIN = 1.8 V,
VOUT = 1.2 V,
IOUT = 300 mA,
COUT = 2.2 µF to 4.7 µF		 48 dB
f = 10 kHz, VIN = 1.8 V,
VOUT = 1.2 V,
IOUT = 300 mA,
COUT = 2.2 µF to 4.7 µF		 30
COUT External output capacitance 2.2 4.7 10 µF
ESR 100 mΩ
RDIS Output auto-discharge resistance LDOA3_DIS[1:0] = 01 80 Ω
LDOA3_DIS[1:0] = 10 180
LDOA3_DIS[1:0] = 11 475
VTT LDO
VIN Power input voltage VDDQ 3.3 V
VOUT DC output voltage Measured at VTTFB pin VIN / 2 V
DC output voltage accuracy Relative to VIN / 2, IOUT = 100 mA,
1.1 V ≤ VIN ≤ 1.5 V		 –10 10 mV
IOUT DC Output Current (RMS Value Over Operation) 1.1 V ≤ VIN ≤ 1.5 V –500 0 500 mA
Pulsed Current (Duty Cycle Limited to Remain Below DC RMS Specification) source(+) and sink(–): LPDDR3 and LPDDR4 OTPs, 1.1 V ≤ VIN ≤ 1.5 V –500 500 mA
source(+) and sink(–): DDR3L OTPs, 1.1 V ≤ VIN ≤ 1.5 V –1800 1800
ΔVOUT/ΔIOUT Load regulation Relative to VIN / 2, IOUT ≤ 10 mA,
1.1 V ≤ VIN ≤ 1.5 V		 –10 10 mV
Relative to VIN / 2, IOUT ≤ 500 mA,
1.1 V ≤ VIN ≤ 1.5 V		 –20 20
Relative to VIN / 2, IOUT ≤ 1200 mA,
1.1 V ≤ VIN ≤ 1.5 V		 –30 30
Relative to VIN / 2, IOUT ≤ 1800 mA,
1.1 V ≤ VIN ≤ 1.5 V		 –40 40
ΔVOUT_TR Load transient regulation DC + AC at sense point, 1.1 V ≤ VIN ≤ 1.5 V,
(IOUT = 0 to 350 mA and 350 mA to 0) AND
(0 to –350 mA and –350 mA to 0) with 1 µs of rise and fall time
COUT = 40 µF		 –5% 5%
IOCP Overcurrent protection Measured with output shorted to ground: OTPs with VTT ILIM = 0.95 A 0.95 A
Measured with output shorted to ground: OTPs with VTT ILIM = 1.8 A 1.8
VTH_PG Power Good deassertion threshold in percentage of target VOUT VOUT rising 110%
VOUT falling 95%
VTH_HYS_PG Power Good reassertion hysteresis entering back into VTH_PG VOUT rising or falling 5%
IQ Total ground current VIN = 1.2 V, IOUT = 0 A 240 µA
ILKG OFF leakage current VIN = 1.2 V, disabled 1 µA
CIN External input capacitance 10 µF
COUT External output capacitance 35 µF
(1) The minimum value must be equal to or greater than 1.62 V.