SLVSAA2D March   2010  – January  2016 TPS65182 , TPS65182B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Data Transmission Timing
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Modes of Operation
      2. 7.3.2  Mode Transistions
      3. 7.3.3  Wake-Up and Power Up Sequencing
      4. 7.3.4  Dependencies Between Rails
      5. 7.3.5  Soft-Start
      6. 7.3.6  VCOM Adjustment
      7. 7.3.7  VPOS and VNEG Supply Tracking
      8. 7.3.8  Fault Handling and Recovery
      9. 7.3.9  Power Good Pin
      10. 7.3.10 Panel Temperature Monitoring
      11. 7.3.11 NTC Bias Circuit
    4. 7.4 Device Functional Modes
      1. 7.4.1 I2C Bus Operation
    5. 7.5 Register Maps
      1. 7.5.1 Thermistor Readout (TMST_VALUE) Register (offset = 0x00h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

The layout guidelines for TPS65182x are as follows:

  • PBKG (Die substrate must connect to VN (–16 V) with short, wide trace. Wide copper trace will improve heat dissipation.
  • Power pad is internally connected to PBKG and must be connected to ground, but connected to VN with a short wide copper trace.
  • Inductor traces must be kept on the PCB top layer free of any vias.
  • Feedback traces must be routed away from any potential noise source to avoid coupling.
  • Output caps must be placed immediately at output pin.
  • VIN pins must be bypassed to ground with low ESR ceramic bypass capacitors.

10.2 Layout Example

TPS65182 TPS65182B Layout_ex_SLVSA76.gif Figure 14. Typical Layout of TPS6518x