SLVSAQ8G February   2011  – September 2017 TPS65185

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Data Transmission
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Wake-Up and Power-Up Sequencing
      2. 8.3.2  Dependencies Between Rails
      3. 8.3.3  Soft Start
      4. 8.3.4  Active Discharge
      5. 8.3.5  VPOS/VNEG Supply Tracking
      6. 8.3.6  V3P3 Power Switch
      7. 8.3.7  VCOM Adjustment
        1. 8.3.7.1 Kick-Back Voltage Measurement
        2. 8.3.7.2 Storing the VCOM Power-Up Default Value in Memory
      8. 8.3.8  Fault Handling And Recovery
      9. 8.3.9  Power Good Pin
      10. 8.3.10 Interrupt Pin
      11. 8.3.11 Panel Temperature Monitoring
        1. 8.3.11.1 NTC Bias Circuit
        2. 8.3.11.2 Hot, Cold, and Temperature-Change Interrupts
        3. 8.3.11.3 Typical Application of the Temperature Monitor
    4. 8.4 Device Functional Modes
      1. 8.4.1 SLEEP
      2. 8.4.2 STANDBY
      3. 8.4.3 ACTIVE
      4. 8.4.4 Mode Transitions
        1. 8.4.4.1 SLEEP → ACTIVE
        2. 8.4.4.2 SLEEP → STANDBY
        3. 8.4.4.3 STANDBY → ACTIVE
        4. 8.4.4.4 ACTIVE → STANDBY
        5. 8.4.4.5 STANDBY → SLEEP
        6. 8.4.4.6 ACTIVE → SLEEP
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Operation
    6. 8.6 Register Maps
      1. 8.6.1  Thermistor Readout (TMST_VALUE) Register (address = 0x00h) [reset = N/A]
      2. 8.6.2  Enable (ENABLE) Register (address = 0x01h) [reset = 0h]
      3. 8.6.3  Voltage Adjustment (VADJ) Register (address = 0x02h) [reset = 23h]
      4. 8.6.4  VCOM 1 (VCOM1) Register (address = 0x03h) [reset = 7Dh]
      5. 8.6.5  VCOM 2 (VCOM2) Register (address = 0x04h) [reset = 04h]
      6. 8.6.6  Interrupt Enable 1 (INT_EN1) Register (address = 0x05h) [reset = 7Fh]
      7. 8.6.7  Interrupt Enable 2 (INT_EN2) Register (address = 0x06h) [reset = FFh]
      8. 8.6.8  Interrupt 1 (INT1) Register (address = 0x07h) [reset = 0h]
      9. 8.6.9  Interrupt 2 (INT2) Register (address = 0x08h) [reset = N/A]
      10. 8.6.10 Power-Up Sequence 0 (UPSEQ0) Register (address = 0x09h) [reset = E4h]
      11. 8.6.11 Power-Up Sequence 1 (UPSEQ1) Register (address = 0x0Ah) [reset = 55h]
      12. 8.6.12 Power-Down Sequence 0 (DWNSEQ0) Register (address = 0x0Bh) [reset = 1Eh]
      13. 8.6.13 Power-Down Sequence 1 (DWNSEQ1) Register (address = 0x0Ch) [reset = E0h]
      14. 8.6.14 Thermistor 1 (TMST1) Register (address = 0x0Dh) [reset = 20h]
      15. 8.6.15 Thermistor 2 (TMST2) Register (address = 0x0Eh) [reset = 78h]
      16. 8.6.16 Power Good Status (PG) Register (address = 0x0Fh) [reset = 0h]
      17. 8.6.17 Revision and Version Control (REVID) Register (address = 0x10h) [reset = 45h]
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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Detailed Description

Overview

The TPS65185x device provides two adjustable LDOs, inverting buck-boost converter, boost converter, thermistor monitoring, and flexible power-up and power-down sequencing. The system can be supplied by a regulated input voltage ranging from 3 V to 6 V. The device is characterized across a –10°C to 85°C temperature range, best suited for personal electronic applications.

The I2C interface provides comprehensive features for using the TPS65185x. All rails can be enabled or disabled. Power-up and power-down sequences can also be programmed through the I2C interface, as well as thermistor configuration and interrupt configuration. Voltage adjustment can also be controlled by the I2C interface.

The adjustable LDOs can supply up to 120 mA (TPS65185) and 200 mA (TPS651851) of current. The default output voltages for each LDO can be adjusted through the I2C interface. LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude. The sum of VLDO1 and VLOD2 is specified to be less than 50 mV.

There are two charge pumps: where VDDH and VEE are 10 mA and 12 mA (TPS65185) and VDDH and VEE are 15 mA and 15 mA (TPS651851) respectively. These charge pumps boost the DC-DC boost converters ±16-V rails to provide a gate channel supply.

The power good functionality is open-drain output, if any of the four power rails (CP1, CP2, LDO1, LDO2) are not in regulation, encounters a fault, or is disabled the pin is pulled low. PWR_GOOD remains low if one of the rails is not enabled by the host and only after all rails are in regulation PWR_GOOD is released to HiZ state (pulled up by external resistor).

The TPS65185x provides circuitry to bias and measure an external NTC to monitor the display panel temperature in a range from –10°C to 85°C with and accuracy of ±1°C from 0°C to 50°C. Temperature measurement are triggered by the controlling host and the last temperature reading is always stored in the TMST_VALUE register. Interrupts are issued when the temperature exceeds the programmable HOT, or drops below the programmable COLD threshold, or when the temperature has changed by more than a user-defined threshold from the baseline value.

This device has the following two package options:

  • TPS65185: 48-Pin, 0.5-mm Pitch, 7 mm × 7 mm × 0.9 mm (QFN) RGZ
  • TPS65185 and TPS651851: 48-Pin, 0.4 mm Pitch, 6 mm × 6 mm × 0.9 mm (QFN) RSL

Functional Block Diagram

TPS65185 TPS651851 tps65185x-functional-block-diagram.gif

Feature Description

Wake-Up and Power-Up Sequencing

The power-up and power-down order and timing is defined by user register settings. The default settings support the E Ink Vizplex panel and typically do not need to be changed.

In SLEEP mode the TPS65185x is completely turned off, the I2C registers are reset, and the device does not accept any I2C transaction. Pull the WAKEUP pin high with the PWRUP pin low and the device enters STANDBY mode which enables the I2C interface. Write to the UPSEQ0 register to define the order in which the output rails are enabled at power-up and to the UPSEQ1 registers to define the power-up delays between rails. Finally, set the ACTIVE bit in the ENABLE register to 1 to execute the power-up sequence and bring up all power rails. Alternatively pull the PWRUP pin high (rising edge).

After the ACTIVE bit has been set, the negative boost converter (VN) is powered up first, followed by the positive boost (VB). The positive boost enable is gated by the internal power-good signal of the negative boost. Once VB is in regulation, it issues an internal power-good signal and after delay time UDLY1 has expired, STROBE1 is issued. The rail assigned to STROBE1 will power up next and after its power-good signal has been asserted and delay time UDLY2 has expired, STROBE2 is issued. The sequence continues until STROBE4 has occurred and the last rail has been enabled.

To power down the device, set the STANDBY bit of the ENABLE register to 1 or pull the PWRUP pin low (falling edge) and the TPS65185x will power down in the order defined by DWNSEQx registers. The delay times DDLY2, DDLY3, and DDLY4 are weighted by a factor of DFCTR which allows the user to space out the power down of the rails to avoid crossing during discharge. DFCTR is located in register DWNSEQ1. The positive boost (VB) is shut down together with the last rail at STROBE4. However, the negative boost (VN) remains up and running for another 100 ms (discharge delay) to allow complete discharge of all rails. After the discharge delay, VN is powered down and the device enters STANDBY or SLEEP mode, depending on the WAKEUP pin.

If either the ACTIVE bit is set or the PWRUP pin is pulled high while the device is powering down, the power-down sequence (STROBE1-4) is completed first, followed by a power-up sequence. VB and VN may or may not be powered down and the discharge delay may be cut short depending on the relative timing of STROBE4 to the new power-up event.

During power-up, if the STANDBY bit is set or the PWRUP pin is pulled low, the power-up sequence is aborted and the power-down sequence starts immediately.

Dependencies Between Rails

Charge pumps, LDOs, and VCOM driver are dependent on the positive and inverting buck-boost converters and several dependencies exist that affect the power-up sequencing. These dependencies are listed below.

  • Inverting buck-boost (DCDC2) must be in regulation before positive boost (DCDC1) can be enabled. Internally, DCDC1 enable is gated by DCDC2 power good.
  • Positive boost (DCDC1) must be in regulation before LDO2 (VNEG) can be enabled. Internally LDO2 enable is gated DCDC1 power-good.
  • Positive boost (DCDC1) must be in regulation before VCOM can be enabled. Internally VCOM enable is gated by DCDC1 power good.
  • Positive boost (DCDC1) must be in regulation before negative charge pump (CP2) can be enabled. Internally CP2 enable is gated by DCDC1 power good.
  • Positive boost (DCDC1) must be in regulation before positive charge pump (CP1) can be enabled. Internally CP1 enable is gated by DCDC1 power good.
  • LDO2 must be in regulation before LDO1 can be enabled. Internally LDO1 enable is gated by LDO2 power good.
TPS65185 TPS651851 pwr_sequence_lvsaq8.gif
TOP: Power-up sequence is defined by assigning strobes to individual rails. STROBE1 is the first strobe to occur after ACTIVE bit is set and STROBE4 is the last event in the sequence. Strobes are assigned to rails in UPSEQ0 register and delays between STROBES are defined in UPSEQ1 register.
BOTTOM: Power-down sequence is independent of power-up sequence. Strobes and delay times for power down sequence are set in DWNSEQ0 and DWNSEQ1 register.
Figure 20. Power-Up and Power-Down Sequence

Soft Start

TPS65185x supports soft start for all rails, that is, inrush current is limited during startup of DCDC1, DCDC2, LDO1, LDO2, CP1 and CP2. If DCDC1 or DCDC2 are unable to reach power-good status within 50 ms, the corresponding UV flag is set in the interrupt registers, the interrupt pin is pulled low, and the device enters STANDBY mode. LDO1, LDO2, positive and negative charge pumps also have a 50-ms power-good time-out limit. If either rail is unable to power up within 50 ms after it has been enabled, the corresponding UV flag is set and the interrupt pin is pulled low. However, the device will remain in ACTIVE mode in this case.

Active Discharge

TPS65185x provides low-impedance discharge paths for the display power rails (VEE, VNEG, VPOS, VDDH, and VCOM) which are enabled whenever the corresponding rail is disabled. The discharge paths are connected to the rails on the PCB which allows adding external resistors to customize the discharge time. However, external resistors are not required.

Active discharge remains enabled for 100 ms after the last rail has been disabled (STROBE4 has been executed). During this time the negative boost converter (VN) remains up. After the discharge delay, VN is shut down and the device enters STANDBY or SLEEP mode, depending on the state of the WAKEUP pin.

VPOS/VNEG Supply Tracking

LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude. The sum of VLDO1 and VLOD2 is specified to be < 50 mV.

V3P3 Power Switch

The integrated power switch is used to cut the 3.3-V supply to the EPD panel and is controlled through the V3P3_EN pin of the ENABLE register. In SLEEP mode the switch is automatically turned off and its output is discharged to ground. The default power-up state is OFF. To turn the switch ON, set the V3P3_ENbit to 1.

VCOM Adjustment

VCOM is the output of a power-amplifier with an output voltage range of 0 V to –5.11 V, adjustable in 10-mV steps. In a typical application VCOM is connected to the VCOM terminal of the EPD panel and the amplifier is controlled through the VCOM_CTRL pin. With VCOM_CTRL high, the amplifier drives the VCOM pin to the voltage specified by the VCOM1 and VCOM2 register. When pulled low, the amplifier turns off and VCOM is actively discharged to ground through VCOM_DIS pin. If active discharge is not desired, simply leave the VCOM_DIS pin open.

For ease of design, the VCOM_CTRL pin may also be tied to the battery or IO supply. In this case, VCOM is enabled with STROBE4 during the power-up sequence and disabled on STROBE1 of the power-down sequence. Therefore VCOM is the last rail to be enabled and the first to be disabled.

Kick-Back Voltage Measurement

TPS65185x can perform a voltage measurement on the VCOM pin to determine the kick-back voltage of the panel. This allows in-system calibration of VCOM. To perform a kick-back voltage measurement, follow these steps:

  • Pull the WAKEUP pin and the PWRUP pin high to enable all output rails.
  • Set the HiZ bit in the VCOM2 register. This puts the VCOM pin in a high-impedance state.
  • Drive the panel with the Null waveform. Refer to E-Ink specification for detail.
  • Set the ACQ bit in the VCOM2 register to 1. This starts the measurement routine.
  • When the measurement is complete, the ACQC (Acquisition Complete) bit in the INT1 register is set and the nINT pin is pulled low.
  • The measurement result is stored in the VCOM[8:0] bits of the VCOM1 and VCOM2 register.

The measurement result is not automatically programmed into nonvolatile memory. Changing the power-up default is described in the following paragraph.

Storing the VCOM Power-Up Default Value in Memory

The power-up default value of VCOM can be user-set and programmed into nonvolatile memory. To do so, write the default value to the VCOM[8:0] bits of the VCOM1 and VCOM2 register, then set the PROG bit in VCOM2 register to 1. First, all power rails are shut down, then the VCOM[8:0] value is committed to nonvolatile memory such that it becomes the new power-up default. Once programming is complete, the PRGC bit in the INT1 register is set and the nINT pin is pulled low. To verify that the new value has been saved properly, first write the VCOM[8:0] bits to 0x000h, then pull the WAKEUP pin low. After the WAKEUP pin is pulled back high, read the VCOM[8:0] bits to verify that the new default value is correct.

TPS65185 TPS651851 vcom_bd1.gif Figure 21. Block Diagram of VCOM Circuit
TPS65185 TPS651851 vcom_calibration_flow_lvsaq8.gif Figure 22. VCOM Calibration Flow

Fault Handling And Recovery

The TPS65185x monitors input/output voltages and die temperature. The device will take action if operating conditions are outside normal limits when the following is encountered:

  • Thermal Shutdown (TSD)
  • Positive Boost Under Voltage (VB_UV)
  • Inverting Buck-Boost Under Voltage (VN_UV)
  • Input Undervoltage Lockout (UVLO)

it shuts down all power rails and enters STANDBY mode. Shut-down follows the order defined by DWNSEQx registers. The exception is VCOM fault witch leads to immediate shutdown of all rails. Once a fault is detected, the PWR_GOOD and nINT pins are pulled low and the corresponding interrupt bit is set in the interrupt register. Power rails cannot be re-enabled unless the interrupt bits have been cleared by reading the INT1 and INT2 register. Alternatively, toggling the WAKEUP pin also resets the interrupt bits. As the PWRUP input is edge sensitive, the host must toggle the PWRUP pin to re-enable the rails through GPIO control, i.e. it must bring the PWRUP pin low before asserting it again. Alternatively rails can be re-enabled through the I2C interface.

Whenever the TPS65185x encounters undervoltage on VNEG (VNEG_UV), VPOS (VPOS_UV), VEE (VEE_UV) or VDDH (VDDH_UV), rails are not shut down but the PWR_GOOD and nINT is pulled low with the corresponding interrupt bit set. The device remains in ACTIVE mode and recovers automatically once the fault has been removed.

Power Good Pin

The power good pin (PWR_GOOD) is an open-drain output that is pulled high (by an external pullup resistor) when all four power rails (CP1, CP2, LDO1, LDO2) are in regulation and is pulled low if any of the rails encounters a fault or is disabled. PWR_GOOD remains low if one of the rails is not enabled by the host and only after all rails are in regulation PWR_GOOD is released to HiZ state (pulled up by external resistor).

Interrupt Pin

The interrupt pin (nINT) is an open drain output that is pulled low whenever one or more of the INT1 or INT2 bits are set. The nINT pin is released (returns to HiZ state) and fault bits are cleared once the register with the set bit has been read by the host. If the fault persists, the nINT pin will be pulled low again after a maximum of 32 µs.

Interrupt events can be masked by resetting the corresponding enable bit in the INT_EN1 and INT_EN2 register, that is, the user can determine which events cause the nINT pin to be pulled low. The status of the enable bits affects the nINT pin only and has no effect on any of the protection and monitoring circuits or the INT1/INT2 bits themselves.

Persisting faults such as thermal shutdown can cause the nINT pin to be pulled low for an extended period of time which can keep the host in a loop trying to resolve the interrupt. If this behavior is not desired, set the corresponding mask bit after receiving the interrupt and keep polling the INT1 and INT2 register to see when the fault condition has disappeared. After the fault is resolved, unmask the interrupt bit again.

Panel Temperature Monitoring

The TPS65185x provides circuitry to bias and measure an external Negative Temperature Coefficient Resistor (NTC) to monitor the display panel temperature in a range from –10°C to 85°C with and accuracy of ±1°C from 0°C to 50°C. Temperature measurement must be triggered by the controlling host and the last temperature reading is always stored in the TMST_VALUE register. Interrupts are issued when the temperature exceeds the programmable HOT, or drops below the programmable COLD threshold, or when the temperature has changed by more than a user-defined threshold from the baseline value. Details are explained in Hot, Cold, and Temperature-Change Interrupts.

NTC Bias Circuit

Figure 23 below shows the block diagram of the NTC bias and measurement circuit. The NTC is biased from an internally generated 2.25-V reference voltage through an integrated 7.307-kΩ bias resistor. A 43-kΩ resistor is connected parallel to the NTC to linearize the temperature response curve. The circuit is designed to work with a nominal 10-kΩ NTC and achieves accuracy of ±1°C from 0°C to 50°C. The voltage drop across the NTC is digitized by a 10-bit SAR ADC and translated into an 8-bit two’s complement by digital per Table 1.

Table 1. ADC Output Value vs Temperature

TEMPERATURE TMST_VALUE[7:0]
< –10°C 1111 0110
–10°C 1111 0110
–9°C 1111 0111
... ...
–2°C 1111 1110
–1°C 1111 1111
0°C 0000 0000
1°C 0000 0001
2°C 0000 0010
... ...
25°C 0001 1001
...
85°C 0101 0101
> 85°C 0101 0101
TPS65185 TPS651851 ntc_bias_lvsaq8.gif Figure 23. NTC Bias and Measurement Circuit

A temperature measurement is triggered by setting the READ_THERM bit of the TMST1 register to 1.During the A/D conversion the CONV_END bit of the TMST1 register reads 0, otherwise it reads 1. At the end of the A/D conversion the EOC bit in the INT2 register is set and the temperature value is available in the TMST_VALUE register.

Hot, Cold, and Temperature-Change Interrupts

Each temperature acquisition is compared against the programmable TMST_HOT and TMST_COLD thresholds and to the baseline temperature, to determine if the display is within allowed operating temperature range and if the temperature has changed by more than a user-defined threshold since the last update. The first temperature reading after the WAKEUP pin has been pulled high automatically becomes the baseline temperature. Any subsequent reading is compared against the baseline temperature. If the difference is equal or greater than the threshold value, an interrupt is issued (DTX bit in register INT1 is set to 1) and the latest value becomes the new baseline. If the difference is less than the threshold value, no action is taken. The threshold value is defined by DT[1:0] bits in the TMST1 register and has a default value of ±2°C. In summary:

  • When the temperature is equal or less than the TMST_COLD[3:0] threshold, the TMST_COLD interrupt bit of the INT1 register is set, and the nINT pin is pulled low.
  • When the temperature is greater than TMST_COLD but lower then TMST_HOT, no action is taken.
  • When the temperature is equal or greater than the TMST_HOT[3:0] threshold, the TMST_HOT interrupt bit of the INT1 register is set, and the nINT pin is pulled low.
  • If the last temperature is different from the baseline temperature by ±2°C (default) or more, the DTX interrupt bit of the INT1 register is set. The latest temperature becomes the new baseline temperature. By default the DTX interrupt is disabled, that is, the nINT pin is not pulled low unless the DTX_EN bit was previously set high.
  • If the last temperature change is less than ±2°C (default), no action is taken.

Typical Application of the Temperature Monitor

In a typical application the temperature monitor and interrupts are used in the following manner:

  • After the WAKEUP pin has been pulled high, the Application Processor (AP) writes 0x80h to the TMST1 register (address 0x0Dh). This starts the temperature measurement.
  • The AP waits for the EOC interrupt. Alternatively the AP can poll the CONV_END bit in register TMST1. This will notify the AP that the A/D conversion is complete and the new temperature reading is available in the TMST_VALUE register (address (0x00h).
  • The AP reads the temperature value from the TMST_VALUE register (address (0x00h).
  • If the temperature changes by ±2°C (default) or more from the first reading, the processor is notified by the DTX interrupt. The A/P may or may not decide to select a different set of wave forms to drive the panel.
  • If the temperature is outside the allowed operating range of the panel, the processor is notified by the THOT and TCOLD interrupts, respectively. It may or may not decide to continue with the page update.
  • Once an overtemperature or undertemperature has been detected, the AP must reset the TMST_HOT_EN or TMST_COLD_EN bits, respectively, to avoid the nINT pin to be continuously pulled low. The TMST_HOT and TMST_COLD interrupt bits then must be polled continuously, to determine when the panel temperature recovers to the normal operating range. Once the temperature has recovered, the TMST_HOT_EN or TMST_COLD_EN bits must be set to 1 again and normal operation can resume.

Device Functional Modes

The TPS65185x has three modes of operation, SLEEP, STANDBY, and ACTIVE. SLEEP mode is the lowest-power mode in which all internal circuitry is turned off. In STANDBY, all power rails are shut down but the device is ready to accept commands through the I2C interface. In ACTIVE mode one or more power rails are enabled.

SLEEP

This is the lowest power mode of operation. All internal circuitry is turned off, registers are reset to default values and the device does not respond to I2C communications. TPS65185x enters SLEEP mode whenever WAKEUP pin is pulled low.

STANDBY

In STANDBY all internal support circuitry is powered up and the device is ready to accept commands through the I2C interface but none of the power rails are enabled. The device enters STANDBY mode when the WAKEUP pin is pulled high and either the PWRUP pin is pulled low or the STANDBY bit is set. The device also enters STANDBY mode if input UVLO, positive boost undervoltage (VB_UV), or inverting buck-boost undervoltage (VN_UV) is detected, thermal shutdown occurs, or the PROG bit is set (see Figure 22).

ACTIVE

The device is in ACTIVE mode when any of the output rails are enabled and no fault condition is present. This is the normal mode of operation while the device is powered up.

Mode Transitions

SLEEP → ACTIVE

WAKEUP pin is pulled high with PWRUP pin high. Rails come up in the order defined by the UPSEQx registers (OK to tie WAKEUP and PWRUP pin together).

SLEEP → STANDBY

WAKEUP pin is pulled high with PWRUP pin low. Rails will remain powered down.

STANDBY → ACTIVE

WAKEUP pin is high and PWRRUP pin is pulled high (rising edge) or the ACTIVE bit is set. Output rails will power up in the order defined by the UPSEQx registers.

ACTIVE → STANDBY

WAKEUP pin is high and STANDBY bit is set or PWRUP pin is pulled low (falling edge). Rails are shut down in the order defined by DWNSEQx registers. Device also enters STANDBY in the event of thermal shutdown (TSD), UVLO, positive boost or inverting buck-boost undervoltage (UV), VCOM fault (VCOMF), or when the PROG bit is set (see Figure 22).

STANDBY → SLEEP

WAKEUP pin is pulled low while none of the output rails are enabled.

ACTIVE → SLEEP

WAKEUP pin is pulled low while at least one output rail is enabled. Rails are shut down in the order defined by DWNSEQx registers.

TPS65185 TPS651851 global_state_lvsaq8.gif
NOTES:
||, & = logic OR, and AND.
(↑), (↓) = rising edge, falling edge
UVLO = Undervoltage Lockout
TSD = Thermal Shutdown
UV = Undervoltage
FAULT = UVLO || TSD || BOOST UV || VCOM fault
Figure 24. Global State Diagram

Programming

I2C Bus Operation

The TPS65185x hosts a slave I2C interface that supports data rates up to 400 kbit/s and auto-increment addressing and is compliant to I2C standard 3.0.

TPS65185 TPS651851 subaddress_i2c_lvsaq8.gif Figure 25. Subaddress in I2C Transmission

The I2C Bus is a communications link between a controller and a series of slave terminals. The link is established using a two-wire bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is sourced from the controller in all cases where the serial data line is bi-directional for data communication between the controller and the slave terminals. Each device has an open drain output to transmit data on the serial data line. An external pullup resistor must be placed on the serial data line to pull the drain output high during data transmission.

Data transmission is initiated with a start bit from the controller as shown in Figure 27. The start condition is recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon reception of a start bit, the device will receive serial data on the SDA input and check for valid address and control information. If the appropriate slave address bits are set for the device, then the device will issue an acknowledge pulse and prepare to receive the register address. Depending on the R/nW bit, the next byte received from the master is written to the addressed register (R/nW = 0) or the device responds with 8-bit data from the register (R/nW = 1). Data transmission is completed by either the reception of a stop condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address, and data words. The I2C interfaces will auto-sequence through register addresses, so that multiple data words can be sent for a given I2C transmission. See Figure 26 and Figure 27 for details.

TPS65185 TPS651851 i2c_data_protocol_lvsaq8.gif
TOP: Master writes data to slave.
BOTTOM: Master reads data from slave.
Figure 26. I2C Data Protocol
TPS65185 TPS651851 i2c_start_stop_lvsaq8.gif Figure 27. I2C Start/Stop/Acknowledge Protocol

Register Maps

Table 2. Register Address Map

Address Acronym Register Name Section
0x00h TMST_VALUE Thermistor value read by ADC Go
0x01h ENABLE Enable/disable bits for regulators Go
0x02h VADJ VPOS/VNEG voltage adjustment Go
0x03h VCOM1 Voltage settings for VCOM Go
0x04h VCOM2 Voltage settings for VCOM + control Go
0x05h INT_EN1 Interrupt enable group1 Go
0x06h INT_EN2 Interrupt enable group2 Go
0x07h INT1 Interrupt group1 Go
0x08h INT2 Interrupt group2 Go
0x09h UPSEQ0 Power-up strobe assignment Go
0x0Ah UPSEQ1 Power-up sequence delay times Go
0x0Bh DWNSEQ0 Power-down strobe assignment Go
0x0Ch DWNSEQ1 Power-down sequence delay times Go
0x0Dh TMST1 Thermistor configuration Go
0x0Eh TMST2 Thermistor hot temp set Go
0x0Fh PG Power good status each rails Go
0x10h REVID Device revision ID information Go

Thermistor Readout (TMST_VALUE) Register (address = 0x00h) [reset = N/A]

Figure 28. TMST_VALUE Register
7 6 5 4 3 2 1 0
TMST_VALUE[7:0]
R-N/A
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3. TMST_VALUE Register Field Descriptions

Bit Field Type Reset Description
7-0 TMST_VALUE R N/A Temperature read-out
F6h = < –10°C
F7h = –9°C
...
FEh = –2°C
FFh = –1°C
0h = 0°C
1h = 1°C
2h = 2°C
...
19h = 25°C
...
55h = > 85°C

Enable (ENABLE) Register (address = 0x01h) [reset = 0h]

Figure 29. ENABLE Register
7 6 5 4 3 2 1 0
ACTIVE STANDBY V3P3_EN VCOM_EN VDDH_EN VPOS_EN VEE_EN VNEG_EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4. ENABLE Register Field Descriptions

Bit Field Type Reset Description
7 ACTIVE R/W 0h STANDBY to ACTIVE transition bit
0h = no effect
1h = Transition from STANDBY to ACTIVE mode. Rails power up as defined by UPSEQx registers
NOTE: After transition bit is cleared automatically
6 STANDBY R/W 0h STANDBY to ACTIVE transition bit
0h = no effect
1h = Transition from STANDBY to ACTIVE mode. Rails power up as defined by DWNSEQx registers
NOTE: After transition bit is cleared automatically. STANDBY bit has priority over ACTIVE.
5 V3P3_EN R/W 0h VIN3P3 to V3P3 switch enable
0h = Switch is OFF
1h = Switch is ON
4 VCOM_EN R/W 0h VCOM buffer enable
0h = Disabled
1h = Enabled
3 VDDH_EN R/W 0h VDDH charge pump enable
0h = Disabled
1h = Enabled
2 VPOS_EN R/W 0h VPOS LDO regulator enable
0h = Disabled
1h = Enabled
NOTE: VPOS cannot be enabled before VNEG is enabled.
1 VEE_EN R/W 0h VEE charge pump enable
0h = Disabled
1h = Enabled
0 VNEG_EN R/W 0h VNEG LDO regulator enable
0h = Disabled
1h = Enabled
NOTE: When VNEG is disabled VPOS will also be disabled.

Voltage Adjustment (VADJ) Register (address = 0x02h) [reset = 23h]

Figure 30. VADJ Register
7 6 5 4 3 2 1 0
Not used Not used Not used Not used Not used VSET[2:0]
R/W-0h R/W-0h R/W-1h R/W-0h R-0h R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5. VADJ Register Field Descriptions

Bit Field Type Reset Description
7 Not used R/W 0h N/A
6 Not used R/W 0h N/A
5 Not used R/W 1h N/A
4 Not used R/W 0h N/A
3 Not used R 0h N/A
2-0 VSET R/W 3h VPOS and VNEG voltage setting
0h = not valid
1h = not valid
2h = not valid
3h = ±15.000 V
4h = ±14.750 V
5h = ±14.500 V
6h = ±14.250 V
7h = reserved

VCOM 1 (VCOM1) Register (address = 0x03h) [reset = 7Dh]

Figure 31. VCOM1 Register
7 6 5 4 3 2 1 0
VCOM[7:0]
R/W-7Dh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. VCOM1 Register Field Descriptions

Bit Field Type Reset Description
7-0 VCOM R/W 7Dh VCOM voltage, least significant byte. See VCOM 2 (VCOM2) Register (address = 0x04h) [reset = 04h] for details.

VCOM 2 (VCOM2) Register (address = 0x04h) [reset = 04h]

Figure 32. VCOM2 Register
7 6 5 4 3 2 1 0
ACQ PROG HiZ AVG[1:0] Not used Not used VCOM[8]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. VCOM2 Register Field Descriptions

Bit Field Type Reset Description
7 ACQ R/W 0h Kick-back voltage acquisition bit
0h = No effect
1h = Starts kick-back voltage measurement routine
NOTE: After measurement is complete bit is cleared automatically and measurement result is reflected in VCOM[8:0] bits.
6 PROG R/W 0h VCOM programming bit
0h = No effect
1h = VCOM[8:0] value is committed to nonvolatile memory and becomes new power-up default
NOTE: After programming bit is cleared automatically and TPS65185x will enter STANDBY mode.
5 HiZ R/W 0h VCOM HiZ bit
1h = VCOM pin is placed into hi-impedance state to allow VCOM measurement
0h = VCOM amplifier is connected to VCOM pin
4-3 AVG R/W 0h Number of acquisitions that is averaged to a single kick-back voltage measurement
0h = 1x
1h = 2x
2h = 4x
3h = 8x
NOTE: When the ACQ bit is set, the state machine repeat the A/D conversion of the kick-back voltage AVD[1:0] times and returns a single, averaged, value to VCOM[8:0]
2 Not used R/W 1h N/A
1 Not used R/W 0h N/A
0 VCOM R/W 0h VCOM voltage adjustment
VCOM = VCOM[8:0] x –10 mV in the range from 0 mV to –5.110 V
0h = –0 mV
1h = –10 mV
2h = –20 mV
...
7Dh = –1250 mV
...
1FEh = –5100 mV
1FFh = –5110 mV

Interrupt Enable 1 (INT_EN1) Register (address = 0x05h) [reset = 7Fh]

Figure 33. INT_EN1 Register
7 6 5 4 3 2 1 0
DTX_EN TSD_EN HOT_EN TMST_HOT_EN TMST_COLD_EN UVLO_EN ACQC_EN PRGC_EN
R-0h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R-1h R-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. INT_EN1 Register Field Descriptions

Bit Field Type Reset Description
7 DTX_EN R 0h Panel temperature-change interrupt enable
0h = Disabled
1h = Enabled
NOTE: Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
6 TSD_EN R/W 1h Thermal shutdown interrupt enable
0h = Disabled
1h = Enabled
NOTE: Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
5 HOT_EN R/W 1h Thermal shutdown early warning enable
0h = Disabled
1h = Enabled
NOTE: Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
4 TMST_HOT_EN R/W 1h Thermistor hot interrupt enable
0h = Disabled
1h = Enabled
NOTE: Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
3 TMST_COLD_EN R/W 1h Thermistor cold interrupt enable
0h = Disabled
1h = Enabled
NOTE: Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
2 UVLO_EN R/W 1h VIN under voltage detect interrupt enable
0h = Disabled
1h = Enabled
NOTE: Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
1 ACQC_EN R 1h VCOM acquisition complete interrupt enable
0h = Disabled
1h = Enabled
NOTE: Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
0 PRGC_EN R 1h VCOM programming complete interrupt enable
0h = Disabled
1h = Enabled
NOTE: Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.

Interrupt Enable 2 (INT_EN2) Register (address = 0x06h) [reset = FFh]

Figure 34. INT_EN2 Register
7 6 5 4 3 2 1 0
VBUVEN VDDHUVEN VNUV_EN VPOSUVEN VEEUVEN VCOMFEN VNEGUVEN EOCEN
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. INT_EN2 Register Field Descriptions

Bit Field Type Reset Description
7 VBUVEN R/W 1h Positive boost converter under voltage detect interrupt enable
0h = Disabled
1h = Enabled
NOTE: Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
6 VDDHUVEN R/W 1h VDDH under voltage detect interrupt enable
0h = Disabled
1h = Enabled
NOTE: Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
5 VNUV_EN R/W 1h Inverting buck-boost converter under voltage detect interrupt enable
0h = Disabled
1h = Enabled
NOTE: Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
4 VPOSUVEN R/W 1h VPOS under voltage detect interrupt enable
0h = Disabled
1h = Enabled
NOTE: Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
3 VEEUVEN R/W 1h VEE under voltage detect interrupt enable
0h = Disabled
1h = Enabled
NOTE: Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
2 VCOMFEN R/W 1h VCOM FAULT interrupt enable
0h = Disabled
1h = Enabled
NOTE: Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
1 VNEGUVEN R/W 1h VNEG under voltage detect interrupt enable
0h = Disabled
1h = Enabled
NOTE: Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
0 EOCEN R/W 1h Temperature ADC end of conversion interrupt enable
0h = Disabled
1h = Enabled
NOTE: Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.

Interrupt 1 (INT1) Register (address = 0x07h) [reset = 0h]

Figure 35. INT1 Register
7 6 5 4 3 2 1 0
DTX TSD HOT TMST_HOT TMST_COLD UVLO ACQC PRGC
R-0h R-N/A R-N/A R-N/A R-N/A R-N/A R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. INT1 Register Field Descriptions

Bit Field Type Reset Description
7 DTX R 0h Panel temperature-change interrupt
0h = No significance
1h = Temperature has changed by 3 deg or more over previous reading
6 TSD R N/A Thermal shutdown interrupt
0h = No fault
1h = Chip is in over-temperature shutdown
5 HOT R N/A Thermal shutdown early warning
0h = No fault
1h = Chip is approaching over-temperature shutdown
4 TMST_HOT R N/A Thermistor hot interrupt
0h = No fault
1h = Thermistor temperature is equal or greater than TMST_HOT threshold
3 TMST_COLD R N/A Thermistor cold interrupt
0h = No fault
1h = Thermistor temperature is equal or less than TMST_COLD threshold
2 UVLO R N/A VIN under voltage detect interrupt
0h = No fault
1h = Input voltage is below UVLO threshold
1 ACQC R 0h VCOM acquisition complete
0h = No significance
1h = VCOM measurement is complete
0 PRGC R 0h VCOM programming complete
0h = No significance
1h = VCOM programming is complete

Interrupt 2 (INT2) Register (address = 0x08h) [reset = N/A]

Figure 36. INT2 Register
7 6 5 4 3 2 1 0
VB_UV VDDH_UV VN_UV VPOS_UV VEE_UV VCOMF VNEG_UV EOC
R-N/A R-N/A R-N/A R-N/A R-N/A R-N/A R-N/A R-N/A
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. INT2 Register Field Descriptions

Bit Field Type Reset Description
7 VB_UV R N/A Positive boost converter undervoltage detect interrupt
0h = No fault
1h = Under-voltage on DCDC1 detected
6 VDDH_UV R N/A VDDH under voltage detect interrupt
0h = No fault
1h = Undervoltage on VDDH charge pump detected
5 VN_UV R N/A Inverting buck-boost converter under voltage detect interrupt
0h = No fault
1h = Undervoltage on DCDC2 detected
4 VPOS_UV R N/A VPOS undervoltage detect interrupt
0h = No fault
1h = Undervoltage on LDO1(VPOS) detected
3 VEE_UV R N/A VEE undervoltage detect interrupt
0h = No fault
1h = Undervoltage on VEE charge pump detected
2 VCOMF R N/A VCOM fault detection
0h = No fault
1h = Fault on VCOM detected (VCOM is outside normal operating range)
1 VNEG_UV R N/A VNEG undervoltage detect interrupt
0h = No fault
1h = Undervoltage on LDO2(VNEG) detected
0 EOC R N/A ADC end of conversion interrupt
0h = No significance
1h = ADC conversion is complete (temperature acquisition is complete)

Power-Up Sequence 0 (UPSEQ0) Register (address = 0x09h) [reset = E4h]

Figure 37. UPSEQ0 Register
7 6 5 4 3 2 1 0
VDDH_UP[1:0] VPOS_UP[1:0] VEE_UP[1:0] VNEG_UP[1:0]
R/W-3h R/W-2h R/W-1h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. UPSEQ0 Register Field Descriptions

Bit Field Type Reset Description
7-6 VDDH_UP R/W 3h VDDH power-up order
0h = Power up on STROBE1
1h = Power up on STROBE2
2h = Power up on STROBE3
3h = Power up on STROBE4
5-4 VPOS_UP R/W 2h VPOS power-up order
0h = Power up on STROBE1
1h = Power up on STROBE2
2h = Power up on STROBE3
3h = Power up on STROBE4
3-2 VEE_UP R/W 1h VEE power-up order
0h = Power up on STROBE1
1h = Power up on STROBE2
2h = Power up on STROBE3
3h = Power up on STROBE4
1-0 VNEG_UP R/W 0h VNEG power-up order
0h = Power up on STROBE1
1h = Power up on STROBE2
2h = Power up on STROBE3
3h = Power up on STROBE4
TPS65185 TPS651851 default_powerseq_lvsaq8.gif Figure 38. Default Power-Up/Down Sequence

Power-Up Sequence 1 (UPSEQ1) Register (address = 0x0Ah) [reset = 55h]

Figure 39. UPSEQ1 Register
7 6 5 4 3 2 1 0
UDLY4[1:0] UDLY3[1:0] UDLY2[1:0] UDLY1[1:0]
R/W-1h R/W-1h R/W-1h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. UPSEQ1 Register Field Descriptions

Bit Field Type Reset Description
7-6 UDLY4 R/W 1h DLY4 delay time set; defines the delay time from STROBE3 to STROBE4 during power up.
0h = 3 ms
1h = 6 ms
2h = 9 ms
3h = 12 ms
5-4 UDLY3 R/W 1h DLY3 delay time set; defines the delay time from STROBE2 to STROBE3 during power up.
0h = 3 ms
1h = 6 ms
2h = 9 ms
3h = 12 ms
3-2 UDLY2 R/W 1h DLY2 delay time set; defines the delay time from STROBE1 to STROBE2 during power up.
0h = 3 ms
1h = 6 ms
2h = 9 ms
3h = 12 ms
1-0 UDLY1 R/W 1h DLY1 delay time set; defines the delay time from VN_PG high to STROBE1 during power up.
0h = 3 ms
1h = 6 ms
2h = 9 ms
3h = 12 ms

Power-Down Sequence 0 (DWNSEQ0) Register (address = 0x0Bh) [reset = 1Eh]

Figure 40. DWNSEQ0 Register
7 6 5 4 3 2 1 0
VDDH_DWN[1:0] VPOS_DWN[1:0] VEE_DWN[1:0] VNEG_DWN[1:0]
R/W-0h R/W-1h R/W-3h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. DWNSEQ0 Register Field Descriptions

Bit Field Type Reset Description
7-6 VDDH_DWN R/W 0h VDDH power-down order
0h = Power down on STROBE1
1h = Power down on STROBE2
2h = Power down on STROBE3
3h = Power down on STROBE4
5-4 VPOS_DWN R/W 1h VPOS power-down order
0h = Power down on STROBE1
1h = Power down on STROBE2
2h = Power down on STROBE3
3h = Power down on STROBE4
3-2 VEE_DWN R/W 3h VEE power-down order
0h = Power down on STROBE1
1h = Power down on STROBE2
2h = Power down on STROBE3
3h = Power down on STROBE4
1-0 VNEG_DWN R/W 2h VNEG power-down order
0h = Power down on STROBE1
1h = Power down on STROBE2
2h = Power down on STROBE3
3h = Power down on STROBE4

Power-Down Sequence 1 (DWNSEQ1) Register (address = 0x0Ch) [reset = E0h]

Figure 41. DWNSEQ1 Register
7 6 5 4 3 2 1 0
DDLY4[1:0] DDLY3[1:0] DDLY2[1:0] DDLY1 DFCTR
R/W-3h R/W-2h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. DWNSEQ1 Register Field Descriptions

Bit Field Type Reset Description
7-6 DDLY4 R/W 3h DLY4 delay time set; defines the delay time from STROBE3 to STROBE4 during power down.
0h = 6 ms
1h = 12 ms
2h = 24 ms
3h = 48 ms
5-4 DDLY3 R/W 2h DLY3 delay time set; defines the delay time from STROBE2 to STROBE3 during power down.
0h = 6 ms
1h = 12 ms
2h = 24 ms
3h = 48 ms
3-2 DDLY2 R/W 0h DLY2 delay time set; defines the delay time from STROBE1 to STROBE2 during power down.
0h = 6 ms
1h = 12 ms
2h = 24 ms
3h = 48 ms
1 DDLY1 R/W 0h DLY2 delay time set; defines the delay time from WAKEUP low to STROBE1 during power down.
0h = 3 ms
1h = 6 ms
0 DFCTR R/W 0h At power-down delay time DLY2[1:0], DLY3[1:0], DLY4[1:0] are multiplied with DFCTR[1:0]
0h = 1x
1h = 16x

Thermistor 1 (TMST1) Register (address = 0x0Dh) [reset = 20h]

Figure 42. TMST1 Register
7 6 5 4 3 2 1 0
READ_THERM Not used CONV_END Not used Not used Not used DT[1:0]
R/W-0h R/W-0h R-1h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. TMST1 Register Field Descriptions

Bit Field Type Reset Description
7 READ_THERM R/W 0h Read thermistor value
0h = No effect
1h = Initiates temperature acquisition
NOTE: Bit is self-cleared after acquisition is completed
6 Not used R/W 0h Not used
5 CONV_END R 1h ADC conversion done flag
0h = Conversion is not finished
1h = Conversion is finished
4 Not used R/W 0h Not used
3 Not used R/W 0h Not used
2 Not used R/W 0h Not used
1-0 DT R/W 0h Panel temperature-change interrupt threshold
0h = 2°C
1h = 3°C
2h = 4°C
3h = 5°C
DTX interrupt is issued when difference between most recent temperature reading and baseline temperature is equal to or greater than threshold value. See Hot, Cold, and Temperature-Change Interrupts for details.

Thermistor 2 (TMST2) Register (address = 0x0Eh) [reset = 78h]

Figure 43. TMST2 Register
7 6 5 4 3 2 1 0
TMST_COLD[3:0] TMST_HOT[3:0]
R/W-7h R/W-8h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. TMST2 Register Field Descriptions

Bit Field Type Reset Description
7-4 READ_THERM R/W 7h Thermistor COLD threshold
0h = –7°C
1h = –6°C
2h = –5°C
3h = –4°C
4h = –3°C
5h = –2°C
6h = –1°C
7h = 0°C
8h = 1°C
9h = 2°C
Ah = 3°C
Bh = 4°C
Ch = 5°C
Dh = 6°C
Eh = 7°C
Fh = 8°C
NOTE: An interrupt is issued when thermistor temperature is equal or less than COLD threshold
3-0 TMST_HOT R/W 8h Thermistor HOT threshold
0h = 42°C
1h = 43°C
2h = 44°C
3h = 45°C
4h = 46°C
5h = 47°C
6h = 48°C
7h = 49°C
8h = 50°C
9h = 51°C
Ah = 52°C
Bh = 53°C
Ch = 54°C
Dh = 55°C
Eh = 56°C
Fh = 57°C
NOTE: An interrupt is issued when thermistor temperature is equal or greater than HOT threshold

Power Good Status (PG) Register (address = 0x0Fh) [reset = 0h]

NOTE: PG pin is pulled hi (HiZ state) when VDDH_PG = VPOS_PG = VEE_PG = VNEG_PG = 1

Figure 44. PG Register
7 6 5 4 3 2 1 0
VB_PG VDDH_PG VN_PG VPOS_PG VEE_PG Not used VNEG_PG Not used
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. PG Register Field Descriptions

Bit Field Type Reset Description
7 VB_PG R 0h Positive boost converter power good
0h = DCDC1 is not in regulation or turned off
1h = DCDC1 is in regulation
6 VDDH_PG R 0h VDDH power good
0h = VDDH charge pump is not in regulation or turned off
1h = VDDH charge pump is in regulation
5 VN_PG R 0h Inverting buck-boost power good
0h = DCDC2 is not in regulation or turned off
1h = DCDC2 is in regulation
4 VPOS_PG R 0h VPOS power good
0h = LDO1(VPOS) is not in regulation or turned off
1h = LDO1(VPOS) is in regulation
3 VEE_PG R 0h VEE power good
0h = VEE charge pump is not in regulation or turned off
1h = VEE charge pump is in regulation
2 Not used R 0h Not used
1 VNEG_PG R 0h VNEG power good
0h = LDO2(VNEG) is not in regulation or turned off
1h = LDO2(VNEG) is in regulation
0 Not used R 0h Not used

Revision and Version Control (REVID) Register (address = 0x10h) [reset = 45h]

Figure 45. REVID Register
7 6 5 4 3 2 1 0
REVID[7:0]
R-45h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. REVID Register Field Descriptions

Bit Field Type Reset Description
7-0 REVID R 45h REVID[7:6] = MJREV
REVID[5:4] = MNREV
REVID[3:0] = VERSION
45h = TPS65185 1p0
55h = TPS65185 1p1
65h = TPS65185 1p2
66h = TPS651851 1p0