SLVSA48A April   2010  – September 2015 TPS65200

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Data Transmission Timing
    7. 6.7 Typical Characteristics
      1. 6.7.1 Switching Charger
      2. 6.7.2 OTG Boost
      3. 6.7.3 LDO
      4. 6.7.4 WLED Boost
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Global State Diagram
      2. 7.3.2 LED Driver Operation
        1. 7.3.2.1 Undervoltage Lockout
        2. 7.3.2.2 Shutdown
        3. 7.3.2.3 Soft-Start Circuit
        4. 7.3.2.4 Open LED Protection
        5. 7.3.2.5 Current Program
        6. 7.3.2.6 Brightness Dimming
        7. 7.3.2.7 Inductor Overcurrent Protection
      3. 7.3.3 HV LDO
      4. 7.3.4 Interrupt Pin
      5. 7.3.5 Current Shunt Monitor
    4. 7.4 Device Functional Modes
      1. 7.4.1 Charge Mode Operation
        1. 7.4.1.1  Input Current Limiting and D+/D- Detection
        2. 7.4.1.2  Bad Adaptor Detection/Rejection (CHBADI)
        3. 7.4.1.3  Input Current Limiting at Start-Up
        4. 7.4.1.4  Charge Profile
        5. 7.4.1.5  Precharge to Fast Charge Threshold (VSHORT)
        6. 7.4.1.6  PWM Controller in Charge Mode
        7. 7.4.1.7  Battery Charging Process
        8. 7.4.1.8  Thermal Regulation and Protection
        9. 7.4.1.9  Safety Timer in Charge and Boost Mode (CH32MI, BST32SI)
        10. 7.4.1.10 Input Voltage Protection in Charge Mode
          1. 7.4.1.10.1 Input Overvoltage Protection (VBUSOVPI)
          2. 7.4.1.10.2 Reverse Current Protection (CHRVPI)
          3. 7.4.1.10.3 Input Voltage Based Dynamic Power Management (CHDPMI)
        11. 7.4.1.11 Battery Protection in Charge Mode
          1. 7.4.1.11.1 Battery Charge Current Limiting
          2. 7.4.1.11.2 Output Overvoltage Protection (CHBATOVPI)
          3. 7.4.1.11.3 Battery Short Protection
        12. 7.4.1.12 Charge Status Output, STAT Pin
      2. 7.4.2 Boost Mode Operation
        1. 7.4.2.1 PWM Controller in Boost Mode
        2. 7.4.2.2 Boost Start Up
        3. 7.4.2.3 PFM Mode at Light Load
        4. 7.4.2.4 Safety Timer in Boost Mode (BST32SI)
        5. 7.4.2.5 Protection in Boost Mode
          1. 7.4.2.5.1 Output Overvoltage Protection (BSTBUSOVI)
          2. 7.4.2.5.2 Output Over-Load Protection (BSTOLI)
          3. 7.4.2.5.3 Battery Voltage Protection (BSTLOWVI, BSTBATOVI)
      3. 7.4.3 High Impedance Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Bus Operation
    6. 7.6 Register Maps
      1. 7.6.1  Control Register (CONTROL)
      2. 7.6.2  Charger Config Register A (CONFIG_A)
      3. 7.6.3  Charger Config Register B (CONFIG_B)
      4. 7.6.4  Charger Config Register C (CONFIG_C)
      5. 7.6.5  Charger Config Register D (CONFIG_D)
      6. 7.6.6  WLED Control Register (WLED)
      7. 7.6.7  Status Register A (STATUS_A)
      8. 7.6.8  Status Register B (STATUS_B)
      9. 7.6.9  Interrupt Register 1 (INT1)
      10. 7.6.10 Interrupt Register 2 (INT2)
      11. 7.6.11 Interrupt Register 3 (INT3)
      12. 7.6.12 Interrupt Mask Register 1 (MASK1)
      13. 7.6.13 Interrupt Mask Register 2 (MASK2)
      14. 7.6.14 Interrupt Mask Register 3 (MASK3)
      15. 7.6.15 Chip ID Register (CHIPID)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN MAX UNIT
Supply voltage (with respect to PGND) VBUS –2 20 V
Input/Output voltage (with respect to PGND) SDA, SCL, DM, DP, SWL, VZERO, VSHRT, CSIN, CSOUT, CSOT, LDO, INT, OTG, VSYS, VSHNT, VDD, VIO, BAT, CTRL –0.3 7 V
PMID, STAT –0.3 20
VDD 6.5
SWC, BOOT –0.7 20
FB,COMP –0.3 3
SWL –0.3 44
Voltage difference between CSIN and CSOUT inputs (VCSIN -VCSOUT) ± 7 V
Output current (average) SWC 1.5 A
Output current (continuous) LDO 100 mA
TA Operating ambient temperature –40 85 °C
TJ Max operating junction temperature 150 °C
TC Max operating case temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VBUS Supply voltage 4 6 V
SWL Output voltage VBAT 39 V

6.4 Thermal Information

THERMAL METRIC(1) TPS65200 UNIT
YFF (DSBGA)
36 PINS
RθJA Junction-to-ambient thermal resistance 54.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.2 °C/W
RθJB Junction-to-board thermal resistance 8.5 °C/W
ψJT Junction-to-top characterization parameter 0.9 °C/W
ψJB Junction-to-board characterization parameter 8.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

VBAT = 3.6 V ±5%, TJ = 27ºC (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CURRENTS
IDISCHARGE Battery discharge current in high Impedance mode (CSIN, CSOUT,SWC, SWL, BAT, VSYS pins) 0°C < TJ < 85°C,
VBAT = 4.2 V		 Charger Hi-Z mode
WLED disabled
Shunt monitor disabled		 2 10 µA
Charger Hi-Z mode
WLED enabled, no load
Shunt monitor disabled		 1800
Charger HiZ mode WLED disabled Shunt monitor enabled 60
IVBUS VBUS supply current VBUS > VBUS(min) Charger PWM ON 10000 µA
Charger PWM OFF 5000
0°C < TJ < 85°C, HZ_MODE = 1 15 
IVBUS_LEAK Leakage current from battery to VBUS pin 0°C < TJ < 85°C, VBAT = 4.2 V HiZ mode 5 µA
VOLTAGE REGULATION
VOREG Output charge voltage Operating in voltage regulation, programmable 3.5 4.44 V
Voltage regulation accuracy TA = 25°C –0.5% 0.5%
Full temperature range –1% 1%
CURRENT REGULATION -FAST CHARGE
IOCHARGE Output charge current VSHRT ≤ VCSOUT < VOREG
VBUS > 5 V, RSNS = 20 mΩ,
LOW_CHG = 0, Programmable		 550 1250 mA
VLOWV ≤ VCSOUT < VOREG,
VBUS > 5 V, RSNS = 20 mΩ,
LOW_CHG = 1		 150 200
CHARGE TERMINATION DETECTION
ITERM Termination charge current VCSOUT > VOREG-VRCH, VBUS > 5 V,
RSNS = 20 mΩ, Programmable		 50 400 mA
Deglitch time for charge termination Both rising and falling, 2-mV overdrive,
tRISE, tFALL = 100 ns		 30 ms
CHARGE CURRENT ACCURACY
VOS, CHRGR Offset voltage, sense voltage amplifier
Charge current accuracy = VOS/(ISETxRSNS)		 TA = 0°C to 85°C –1 1 mV
BAD ADAPTOR DETECTION
VIN(MIN) Input voltage lower limit Bad adaptor detection, VBUS falling 3.6 3.8 4 V
Deglitch time for VBUS rising above VIN(MIN) Rising voltage, 2-mV over drive,
tRISE = 100 ns		 30 ms
Hysteresis for VIN(MIN) VBUS rising 100 200 mV
IADET Current source to GND During bad adaptor detection 20 30 40 mA
TINT Detection interval Input power source detection 2 s
INPUT BASED DYNAMIC POWER MANAGEMENT
VIN_LOW The threshold when input based DPM loop kicks in Charge mode, programmable 4.2 4.76 V
DPM loop kick-in threshold tolerance –2% 2%
INPUT CURRENT LIMITING
IIN_LIMIT Input current limiting threshold IIN_LIMIT = 100 mA 88 93 98 mA
IIN_LIMIT = 500 mA 450 475 500
IIN_LIMIT = 975 mA 875 925 975
VDD REGULATOR
VDD Internal bias regulator voltage VBUS > VIN(min) or VSYS > VBATMIN,
IVDD = 1 mA, CVDD = 1 μF		 2 6.5 V
VDD output short current limit 30 mA
Voltage from BST pin to SWC pin During charge or boost operation 6.5 V
BATTERY RECHARGE THRESHOLD
VRCH Recharge threshold voltage Below VOREG 100 130 160 mV
Deglitch time VCSOUT decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive		 130 ms
STAT OUTPUT
VOL(STAT) Low-level output saturation voltage IO = 10 mA, sink current 0.4 V
High-level leakage current Voltage on STAT pin is 5 V 1 µA
REVERSE PROTECTION COMPARATOR
VREV Reverse protection threshold, VBUS-VCSOUT 2.3 V ≤ VCSOUT ≤ VOREG, VBUS falling 0 40 100 mV
VREV-EXIT Reverse protection exit hysteresis 2.3 V ≤ VCSOUT ≤ VOREG 140 200 260 mV
Deglitch time for VBUS rising above VREV + VREV_EXIT Rising voltage 30 ms
VBUS UVLO
VUVLO IC active threshold voltage VBUS rising 3.05  3.3 3.55 V
VUVLO_HYS IC active hysteresis VBUS falling from above VUVLO 120 150 mV
PWM
fPWM PWM frequency, charger 3 MHz
RDSON Internal top reverse blocking
MOSFET on-resistance		 IIN_LIMIT = 500 mA,
Measured from VBUS to PMID		 180 mΩ
Internal top N-channel Switching
MOSFET on-resistance		 Measured from PMID to SWC 120
Internal bottom N-channel
MOSFET on-resistance		 Measured from SW to PGND 150
DMAX Maximum duty cycle 99.5%
DMIN Minimum duty cycle 0%
Synchronous mode to nonsynchronous mode transition current threshold(1) Low-side MOSFET
cycle-by-cycle current sensing		 100 mA
BOOST MODE OPERATION FOR VBUS (OPA_MODE=1, HZ_MODE=0)
VBUS_B Boost output voltage (to pin VBUS) 2.5 V < VBUS < 4.5 V; Including line and load regulation over full temp range 4.75 5 5.25 V
IBO Maximum output current for boost VBUS_B = 5 V, 2.5 V < VBUS < 4.5 V 200 mA
IBLIMIT Cycle by cycle current limit for boost VBUS_B = 5 V, 2.5 V < VSYS < 4.5 V 1 A
VBUSOVP Overvoltage protection threshold for boost (VBUS pin) Threshold over VBUS to turn off converter during boost 5.8 6 6.2 V
VBUSOVP hysteresis VBUS falling from above VBUSOVP 200  mV
VBATMAX Maximum battery voltage for boost VSYS rising edge during boost 4.75 4.9 5.05 V
VBATMAX hysteresis VSYS falling from above VBATMAX 200 mV
VBATMIN Minimum battery voltage for boost (VSYS pin) During boosting 2.5 V
Before boost starts 2.9 3.05
Boost output resistance at high impedance mode (From VBUS to PGND) HZ_MODE = 1 500 kΩ
CHARGER PROTECTION
VOVP-IN_USB Input VBUSOVP threshold voltage Threshold over VBUS to turn off converter during charge 6.3 6.5 6.7 V
VOVP_IN_USB hysteresis VBUS falling from above VOVP_IN 140 mV
VOVP Battery OVP threshold voltage VCSOUT threshold over VOREG to turn off charger during charge (% VOREG) 110% 117% 121%
VOVP hysteresis Lower limit for VCSOUT falling from > VOVP (% VOREG) 11%
ILIMIT Cycle-by-cycle current limit for charge Charge mode operation 1.8 2.4 3 A
VSHORT Trickle to fast charge threshold VCSOUT rising, VSHRT connected to VDD 2 2.1 2.2 V
Resistor connected from VSHRT to GND 1.8 VBUS – 0.7  V
Internal current source connected to VSHRT pin 9.4 10 10.6 µA
VSHORT  hysteresis VCSOUT falling from above VSHORT 100 mV
Enable threshold for internal VSHORT reference percentage of VDD 90%
ISHORT Trickle charge charging current VCSOUT ≤ VSHORT 20 30 40 mA
TCF Thermal regulation threshold Charge current begins to taper down 120 °C
T32S Time constant for the 32-second timer 32 second mode 32  s
WLED VOLTAGE AND CURRENT CONTROL
VREF Voltage feedback regulation voltage 198 203 208 mV
VREF_PWM Voltage feedback regulation voltage under brightness control VFB[4:0] = 01110 (VFB = 25%) 47 50 53 mV
VFB[4:0] = 01110 (VFB = 10%) 17 20 23
fCTRL PWM dimming frequency 1 100 kHz
tCNTRL, MIN Minimum on-time for PWM dimming pulse 2.2 µs
IFB Voltage feedback input bias current VFB = 200 mV 1 µA
fPWM PWM frequency, WLED boost 600 kHz
Dmax Maximum duty cycle VFB = 100 mV 90% 93%
tmin_on Minimum 0N pulse width 40 ns
L Inductor 10 22 µH
COUT Output capacitor 0.47 10 µF
WLED POWER SWIITCH
RDS(on) N-channel MOSFET on-resistance VSYS = 3.6 V 300 600 mΩ
ILN_NFET N-channel leakage current VSWL = 30 V, TA = 25°C 1 µA
WLED PROTECTION
VUVLO Under Voltage Lock Out (VSYS pin) VSYS falling 2.2 2.5  V
UVLO hysteresis 70 mV
VOVP Overvoltage Protection threshold 35 37 39 V
ILIM N-Channel MOSFET current limit D = Dmax 560 700 840 mA
ILIM_Start Startup current limit D = Dmax 400 mA
tHALF_LIM Time step for half current limit 5 ms
tREF VREF filter time constant 180 µs
tstep VREF ramp up time 213 µs
CURRENT SHUNT MONITOR
VCM Common-mode input range VCSIN = VCSOUT –0.3 7 V
CMR Common-mode rejection VCSIN = 2.7 V to 5 V, VCSIN – VCSOUT = 0 mV 100 dB
VOS, CSM Offset-voltage, referred to input TA = 0°C to 60°C –75 75 µV
TA = -20°C to 85°C –85 85
G Gain 25  V/V
Gain error –1% 1%
VSHNT Swing to positive power supply rail (VSYS) VSYS - VSHNT 100  mV
Swing to GND VSHNT - VGND 100
GBW Bandwidth CLOAD = 10 pF 9 kHz
IVZERO VZERO bias current TA = -20°C to 85°C 10 nA
VZERO Swing to positive power supply rail (VSYS) VSYS – VZERO 1.5  V
Swing to GND VZERO - VGND 0.7
VUVLO Undervoltage lockout (VSYS pin) VSYS falling 2.2 2.5  V
UVLO hysteresis 70 mV
LDO
VLDO LDO Output Voltage VIN = 5.5V 4.8 4.9 5 V
PSRR f = 100 Hz, CLDO = 1.0 μF 60 dB
ILDO Maximum LDO Output Current 60 mA
VDO Dropout Voltage VIN = 4.5 V, ILDO = 50 mA 100 250 mV
D+/D- DETECTION
VDP_SCR D+ voltage source 0.5 0.6 0.7 V
D+ voltage source output current 250 µA
IDM_SINK D- current sink 50 100 150 µA
CI Input capacitance DM pin, switch open 4.5 5 pF
DP pin, switch open 4.5 5
II Input leakage DM pin, switch open –1 1 µA
DP pin, switch open –1 1
VDP_LOW DP low comparator threshold 0.8 V
VDM_HIGH DM high comparator threshold 0.8 V
VDM_LOW DM low comparator threshold 475 mV
LOGIC LEVELS AND TIMING CHARTERISTICS (SCL, SDA, CTRL, INT)
VOL Output low threshold level IO = 3 mA, sink current (SDA, INT) 0.4 V
Input low threshold level 0.4
Input high threshold level 1.2
I(bias) Input bias current (SCL, SDA, INT) VIO = 1.8 V 1 µA
fSCL SCL clock frequency 400 kHz
RCTRL CTRL pulldown resistor 400 800 1600 kΩ
tOFF CTRL pulse width to shutdown CTRL high to low 2.5 ms
7-bit slave address 1101 010
OSCILLATOR
fOSC Oscillator frequency 3 MHz
Frequency accuracy TA = –40°C to 85°C –10% 10%
THERMAL SHUTDOWN
TSHTDWN Thermal trip point 165 °C
Thermal hysteresis 10
(1) Bottom N-channel MOSFET always turns on for approximately 60 ns and then turns off if current is too low.

6.6 Data Transmission Timing

VBAT = 3.6 ±5%, TA = 25 ºC, CL = 100 pF (unless otherwise noted)
MIN NOM MAX UNIT
f(SCL) Serial clock frequency Standard mode 100 KHz
Fast mode 400
t(BUF) Bus free time between stop and start condition SCL = 100 kHz 4.7 µs
SCL = 400 kHz 1.3
t(SP) Tolerable spike width on bus SCL = 100 kHz 50 ns
SCL = 400 kHz
tLOW SCL low time SCL = 100 kHz 4.7 µs
SCL = 400 kHz 1.3
tHIGH SCL high time SCL = 100 kHz 4 µs
SCL = 400 kHz 0.6
tS(DAT) SDA → SCL setup time SCL = 100 kHz 250 ns
SCL = 400 kHz 100
tS(STA) Start condition setup time SCL = 100 kHz 4.7 µs
SCL = 400 kHz 0.6
tS(STO) Stop condition setup time SCL = 100 kHz 4 µs
SCL = 400 kHz 0.6
tH(DAT) SDA → SCL hold time SCL = 100 kHz 0 3.45 µs
SCL = 400 kHz 0 0.9
tH(STA) Start condition hold time SCL = 100 kHz 4 µs
SCL = 400 kHz 0.6
tr(SCL) Rise time of SCL Signal SCL = 100 kHz 1000 ns
SCL = 400 kHz 300
tf(SCL) Fall time of SCL Signal SCL = 100 kHz 300 ns
SCL = 400 kHz 300
tr(SDA) Rise time of SDA Signal SCL = 100 kHz 1000 ns
SCL = 400 kHz 300
tf(SDA) Fall time of SDA Signal SCL = 100 KHz 300 ns
SCL = 400 kHz 300
TPS65200 i2c_data_lvsa48.gif Figure 1. I2C Data Transmission Timing

6.7 Typical Characteristics

TA = 25°C, unless otherwise specified.

6.7.1 Switching Charger

TPS65200 fig3_lvsa48.gif
VBUS = 5 V ICHARGE = 150 mA
Figure 2. PWM Charge Operation
TPS65200 fig11_lvsa48.gif
VBUS = 5.5 V RIN = 60 Ω VBAT = 3 V (#165)
Figure 4. Bad Adaptor Detection
TPS65200 fig13_lvsa48.gif
ICHARGE = 950 mA IIN_limit = 975 mA VSHORT = 2.8 V
Figure 6. Precharge Curve
TPS65200 fig15_lvsa48.gif
VBUS = 5.5 V
Figure 8. Charger Efficiency
TPS65200 fig4_lvsa48.gif
VBUS = 5 V ICHARGE = 150 mA
Figure 3. PWM Charge Operation
TPS65200 fig12_lvsa48.gif
1500 mAh Li-ion 5.55 Whr ICHARGE = 950 mA
IIN_limit = 975 mA
Figure 5. Charging Curve
TPS65200 fig14_lvsa48.gif Figure 7. Effective Dropout Voltage

6.7.2 OTG Boost

TPS65200 fig16_lvsa48.gif
VBAT = 3.8 V ILOAD = 200 mA
Figure 9. Start Up
TPS65200 fig18_lvsa48.gif
VBAT = 3.8 V ILOAD = 1 mA
Figure 11. PWM Boost Operation
TPS65200 fig20_lvsa48.gif
VBAT = 3.8 V ILOAD = 200 mA
Figure 13. PWM Boost Operation
TPS65200 fig22_lvsa48.gif
VBAT = 3.8 V ILOAD = 200 mA
Figure 15. I2C Controlled Voltage Step
TPS65200 fig17_lvsa48.gif
VBAT = 3.8 V ILOAD = 200 mA
Figure 10. Shutdown
TPS65200 fig19_lvsa48.gif
VBAT = 3.8 V ILOAD = 30 mA
Figure 12. PWM Boost Operation
TPS65200 fig21_lvsa48.gif
VBAT = 3.8 V ILOAD = 5 mA - 200 mA
Figure 14. Transient Response
TPS65200 fig23_lvsa48.gif
VBAT = 3.8 V ILOAD = 200 mA
Figure 16. I2C Controlled Voltage Step

6.7.3 LDO

TPS65200 fig24_lvsa48.gif Figure 17. Turnon Delay
TPS65200 fig26_lvsa48.gif
Charger = ON at 950 mA VBUS = 5.5 V
Figure 19. Start-Up
TPS65200 fig28_lvsa48.gif
50 mA Load, Charger = ON at 950 mA VBUS = 5.5 V
Figure 21. Start-Up
TPS65200 fig30_lvsa48.gif
Charger OFF ILOAD = 5 mA to 50 mA VBUS = 5.5 V
Figure 23. Transient Response
TPS65200 fig25_lvsa48.gif Figure 18. Turnoff Delay
TPS65200 fig27_lvsa48.gif
Charger = ON at 950 mA VBUS = 5.5 V
Figure 20. Shutdown
TPS65200 fig29_lvsa48.gif
50 mA Load, Charger = ON at 950 mA VBUS = 5.5 V
Figure 22. Shutdown
TPS65200 fig31_lvsa48.gif
VBUS = 5.5 V
Figure 24. OTG Boost Efficiency

6.7.4 WLED Boost

TPS65200 fig32_lvsa48.gif
VBAT = 3.8 V VFB = 200 mV 7 LEDs
Figure 25. Start-Up
TPS65200 fig34_lvsa48.gif
VBAT = 4.2 V VFB = 200 mV 7 LEDs
Figure 27. PWM Operation
TPS65200 fig36_lvsa48.gif
VBAT = 3 V VFB = 200 mV 7 LEDs
Figure 29. PWM Operation
TPS65200 fig38_lvsa48.gif
50% Duty Cycle VBAT = 3.8 V VFB = 200 mV
7 LEDs
Figure 31. PWM Dimming
TPS65200 fig40_lvsa48.gif
VBAT = 3.3 V
Figure 33. Efficiency
TPS65200 fig42_lvsa48.gif
VBAT = 3.8 V FPWM = 5 kHz 7 LEDs
Figure 35. WLED Dimming Linearity
TPS65200 fig33_lvsa48.gif
VBAT = 3.8 V VFB = 200 mV 7 LEDs
Figure 26. Shutdown
TPS65200 fig35_lvsa48.gif
VBAT = 4.2 V VFB = 20 mV 7 LEDs
Figure 28. PWM Operation
TPS65200 fig37_lvsa48.gif
VBAT = 3 V VFB = 20 mV 7 LEDs
Figure 30. PWM Operation
TPS65200 fig39_lvsa48.gif
VBAT = 3.8 V VFB = 200 mV 7 LEDs (#162)
Figure 32. Open LED Protection
TPS65200 fig41_lvsa48.gif
6 LEDs
Figure 34. Efficiency