JAJSF01I November   2011  – March 2018 TPS65217

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Wake-Up and Power-Up Sequencing
        1. 8.3.1.1 Power-Up Sequencing
        2. 8.3.1.2 Power-Down Sequencing
        3. 8.3.1.3 Special Strobes (STROBE 14 and 15)
      2. 8.3.2  Power Good
        1. 8.3.2.1 LDO1, LDO2 Power-Good (LDO_PGOOD)
        2. 8.3.2.2 Primary Power-Good (PGOOD)
        3. 8.3.2.3 Load Switch PGOOD
      3. 8.3.3  Push-Button Monitor (PB_IN)
      4. 8.3.4  nWAKEUP Pin (nWAKEUP)
      5. 8.3.5  Power Enable Pin (PWR_EN)
      6. 8.3.6  Reset Pin (nRESET)
      7. 8.3.7  Interrupt Pin (nINT)
      8. 8.3.8  Analog Multiplexer
      9. 8.3.9  Battery Charger and Power Path
        1. 8.3.9.1 Shorted or Absent Battery (VBAT < 1.5 V)
        2. 8.3.9.2 Dead Battery (1.5 V < VBAT < VUVLO)
        3. 8.3.9.3 Good Battery (VBAT > VUVLO)
        4. 8.3.9.4 AC and USB Input Discharge
      10. 8.3.10 Battery Charging
      11. 8.3.11 Precharge
      12. 8.3.12 Charge Termination
      13. 8.3.13 Battery Detection and Recharge
      14. 8.3.14 Safety Timer
        1. 8.3.14.1 Dynamic Timer Function
        2. 8.3.14.2 Timer Fault
      15. 8.3.15 Battery-Pack Temperature Monitoring
      16. 8.3.16 DC/DC Converters
        1. 8.3.16.1 Operation
        2. 8.3.16.2 Output Voltage Setting
        3. 8.3.16.3 Power-Save Mode and Pulse-Frequency Modulation (PFM)
        4. 8.3.16.4 Dynamic Voltage Positioning
        5. 8.3.16.5 100% Duty-Cycle Low-Dropout Operation
        6. 8.3.16.6 Short-Circuit Protection
        7. 8.3.16.7 Soft Start
      17. 8.3.17 Standby LDO Regulators (LDO1, LDO2)
      18. 8.3.18 Load Switches or LDO Regulators (LS1 or LDO3, LS2 or LDO4)
      19. 8.3.19 White LED Driver
    4. 8.4 Device Functional Modes
      1. 8.4.1 PMIC States
        1. 8.4.1.1 OFF State
        2. 8.4.1.2 ACTIVE State
        3. 8.4.1.3 SLEEP State
        4. 8.4.1.4 RESET State
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Operation
      2. 8.5.2 Password Protection
        1. 8.5.2.1 Level1 Protection
        2. 8.5.2.2 Level2 Protection
      3. 8.5.3 Resetting of Registers to Default Values
    6. 8.6 Register Maps
      1. 8.6.1  Register Address Map
      2. 8.6.2  Chip ID Register (CHIPID) (Address = 0x00) [reset = X]
        1. Table 2. CHIPID Register Field Descriptions
      3. 8.6.3  Power Path Control Register (PPATH) (Address = 0x01) [reset = 0x3D]
        1. Table 3. PPATH Register Field Descriptions
      4. 8.6.4  Interrupt Register (INT) (Address = 0x02) [reset = 0x80]
        1. Table 4. INT Register Field Descriptions
      5. 8.6.5  Charger Configuration Register 0 (CHGCONFIG0) (Address = 0x03) [reset = 0x00]
        1. Table 5. CHGCONFIG0 Register Field Descriptions
      6. 8.6.6  Charger Configuration Register 1 (CHGCONFIG1) (Address = 0x04) [reset = 0xB1]
        1. Table 6. CHGCONFIG1 Register Field Descriptions
      7. 8.6.7  Charger Configuration Register 2 (CHGCONFIG2) (Address = 0x05) [reset = 0x80]
        1. Table 7. CHGCONFIG2 Register Field Descriptions
      8. 8.6.8  Charger Configuration Register 3 (CHGCONFIG3) (Address = 0x06) [reset = 0xB2]
        1. Table 8. CHGCONFIG3 Register Field Descriptions
      9. 8.6.9  WLED Control Register 1 (WLEDCTRL1) (Address = 0x07) [reset = 0xB1]
        1. Table 9. WLEDCTRL1 Register Field Descriptions
      10. 8.6.10 WLED Control Register 2 (WLEDCTRL2) (Address = 0x08) [reset = 0x00]
        1. Table 10. WLEDCTRL2 Register Field Descriptions
      11. 8.6.11 MUX Control Register (MUXCTRL) (Address = 0x09) [reset = 0x00]
        1. Table 11. MUXCTRL Register Field Descriptions
      12. 8.6.12 Status Register (STATUS) (Address = 0x0A) [reset = 0x00]
        1. Table 12. STATUS Register Field Descriptions
      13. 8.6.13 Password Register (PASSWORD) (Address = 0x0B) [reset = 0x00]
        1. Table 13. Password Register (PASSWORD) Field Descriptions
      14. 8.6.14 Power Good Register (PGOOD) (Address = 0x0C) [reset = 0x00]
        1. Table 14. PGOOD Register Field Descriptions
      15. 8.6.15 Power-Good Control Register (DEFPG) (Address = 0x0D) [reset = 0x0C]
        1. Table 15. DEFPG Register Field Descriptions
      16. 8.6.16 DCDC1 Control Register (DEFDCDC1) (Address = 0x0E) [reset = X]
        1. Table 16. DEFDCDC1 Register Field Descriptions
      17. 8.6.17 DCDC2 Control Register (DEFDCDC2) (Address = 0x0F) [reset = X]
        1. Table 17. DEFDCDC2 Register Field Descriptions
      18. 8.6.18 DCDC3 Control Register (DEFDCDC3) (Address = 0x10) [reset = 0x08]
        1. Table 18. DEFDCDC3 Register Field Descriptions
      19. 8.6.19 Slew-Rate Control Register (DEFSLEW) (Address = 0x11) [reset = 0x06]
        1. Table 19. DEFSLEW Register Field Descriptions
      20. 8.6.20 LDO1 Control Register (DEFLDO1) (Address = 0x12) [reset = 0x09]
        1. Table 20. DEFLDO1 Register Field Descriptions
      21. 8.6.21 LDO2 Control Register (DEFLDO2) (Address = 0x13) [reset = 0x38]
        1. Table 21. DEFLDO2 Register Field Descriptions
      22. 8.6.22 Load Switch1 or LDO3 Control Register (DEFLS1) (Address = 0x14) [reset = X]
        1. Table 22. DEFLS1 Register Field Descriptions
      23. 8.6.23 Load Switch2 or LDO4 Control Register (DEFLS2) (Address = 0x15) [reset = X]
        1. Table 23. DEFLS2 Register Field Descriptions
      24. 8.6.24 Enable Register (ENABLE) (Address = 0x16) [reset = 0x00]
        1. Table 24. ENABLE Register Field Descriptions
      25. 8.6.25 UVLO Control Register (DEFUVLO) (Address = 0x18) [reset = 0x03]
        1. Table 25. DEFUVLO Register Field Descriptions
      26. 8.6.26 Sequencer Register 1 (SEQ1) (Address = 0x19) [reset = X]
        1. Table 26. SEQ1 Register Field Descriptions
      27. 8.6.27 Sequencer Register 2 (SEQ2) (Address = 0x1A) [reset = X]
        1. Table 27. SEQ2 Register Field Descriptions
      28. 8.6.28 Sequencer Register 3 (SEQ3) (Address = 0x1B) [reset = X]
        1. Table 28. SEQ3 Register Field Descriptions
      29. 8.6.29 Sequencer Register 4 (SEQ4) (Address = 0x1C) [reset = 0x40]
        1. Table 29. SEQ4 Register Field Descriptions
      30. 8.6.30 Sequencer Register 5 (SEQ5) (Address = 0x1D) [reset = X]
        1. Table 30. SEQ5 Register Field Descriptions
      31. 8.6.31 Sequencer Register 6 (SEQ6) (Address = 0x1E) [reset = 0x00]
        1. Table 31. SEQ6 Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Filter Design (Inductor and Output Capacitor)
          1. 9.2.2.1.1 Inductor Selection for Buck Converters
          2. 9.2.2.1.2 Output Capacitor Selection
          3. 9.2.2.1.3 Input Capacitor Selection
        2. 9.2.2.2 5-V Operation Without a Battery
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.1.2 Power-Down Sequencing

By default, power-down sequencing follows the reverse power-up sequence. When the power-down sequence is triggered, STROBE7 occurs first, and any rail assigned to STROBE7 is shut down. After a delay time of DLY6, STROBE6 occurs, and any rail assigned to STROBE6 is shut down. The sequence continues until all strobes have occurred and all DLYx times have been executed.

In some applications, all rails may be required to shut down at the same time with no delay between rails. Set the INSTDWN bit in the SEQ6 register to bypass all delay times and shut-down all rails at the same time when the power-down sequence is triggered.

A power-down sequence is executed if one of the following events occurs:

  • The SEQDWN bit is set.
  • The PWR_EN pin is pulled low.
  • The push-button is pressed for more than 8 s.
  • The nRESET pin is pulled low.
  • A fault occurs in the device (either an OTS, UVLO, or PGOOD failure).
  • The PWR_EN pin is not asserted (pulled high) within 5 s of a power-up event and the OFF bit is set to 1b.

When the device goes from the ACTIVE to the OFF state, any rail not controlled by the sequencer is shut down after the power-down sequencer is complete. When the device goes from the ACTIVE to the SLEEP state, any rail not controlled by the power-down sequencer stays in its present state.

TPS65217 pwr_dwn_seq_lvsb64.gifFigure 5. Power-Down Sequence from ON State to OFF State (All Rails Turned OFF)
TPS65217 pwr_dwn_seq2_lvsb64.gif
STROBE14 and STROBE15 are omitted to let the LDO1 or LDO2 regulators stay ON.
Figure 6. Power-Down Sequence from ON State to SLEEP State