JAJSI26A November   2019  – February 2021 TPS6521815

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
    1. 3.1 概略回路図
  4. Revision History
  5. 概要 (続き)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Wake-Up and Power-Up and Power-Down Sequencing
        1. 8.3.1.1  Power-Up Sequencing
        2. 8.3.1.2  Power-Down Sequencing
        3. 8.3.1.3  Strobe 1 and Strobe 2
        4. 8.3.1.4  Supply Voltage Supervisor and Power-Good (PGOOD)
        5. 8.3.1.5  Backup Supply Power-Good (PGOOD_BU)
        6. 8.3.1.6  Internal LDO (INT_LDO)
        7. 8.3.1.7  Current Limited Load Switches
          1. 8.3.1.7.1 Load Switch 1 (LS1)
          2. 8.3.1.7.2 Load Switch 2 (LS2)
          3. 8.3.1.7.3 Load Switch 3 (LS3)
        8. 8.3.1.8  LDO1
        9. 8.3.1.9  Coin Cell Battery Voltage Acquisition
        10. 8.3.1.10 UVLO
        11. 8.3.1.11 Power-Fail Comparator
        12. 8.3.1.12 Battery-Backup Supply Power-Path
        13. 8.3.1.13 DCDC3 and DCDC4 Power-Up Default Selection
        14. 8.3.1.14 I/O Configuration
          1. 8.3.1.14.1 Configuring GPO2 as Open-Drain Output
          2. 8.3.1.14.2 Using GPIO3 as Reset Signal to DCDC1 and DCDC2
        15. 8.3.1.15 Push Button Input (PB)
          1. 8.3.1.15.1 Signaling PB-Low Event on the nWAKEUP Pin
          2. 8.3.1.15.2 Push Button Reset
        16. 8.3.1.16 AC_DET Input (AC_DET)
        17. 8.3.1.17 Interrupt Pin (INT)
        18. 8.3.1.18 I2C Bus Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
      2. 8.4.2 OFF
      3. 8.4.3 ACTIVE
      4. 8.4.4 SUSPEND
      5. 8.4.5 RESET
    5. 8.5 Programming
      1. 8.5.1 Programming Power-Up Default Values
    6. 8.6 Register Maps
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Applications Without Backup Battery
      2. 9.1.2 Applications Without Battery Backup Supplies
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Filter Design
        2. 9.2.2.2 Inductor Selection for Buck Converters
        3. 9.2.2.3 Output Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT VOLTAGE AND CURRENTS
VIN_BIASInput supply voltage rangeNormal operation2.75.5V
EEPROM programming4.55.5
Deglitch time5ms
IOFFOFF state current, total current into IN_BIAS, IN_DCDCx, IN_LDO1, IN_LSVIN = 3.6 V; All rails disabled.
TJ = 0°C to 85°C
5µA
ISUSPENDSUSPEND current, total current into IN_BIAS, IN_DCDCx, IN_LDO1, IN_LSVIN = 3.6 V; DCDC3 enabled, low-power mode, no load.
All other rails disabled.
TJ = 0°C to 105°C
220µA
SYS_BU
VSYS_BUSYS_BU voltage rangePowered from VIN_BU or VCC2.25.5V
CSYS_BURecommended SYS_BU capacitorCeramic, X5R or X7R, see Table 9-3.1µF
ToleranceCeramic, X5R or X7R, rated voltage ≥ 6.3 V–20%20%
INT_LDO
VINT_LDOOutput voltage2.5V
DC accuracyIOUT < 10 mA–2%2%
IOUTOutput current rangeMaximum allowable external load010mA
ILIMITShort circuit current limitOutput shorted to GND23mA
tHOLDHold-up timeMeasured from VINT_LDO = to VINT_LDO = 1.8 V
All rails enabled before power off,
IN_BIAS tied to IN_DCDC1-4, IN_LDO1

VIN_BIAS = 2.8 V to 0 V in < 5 µs
No external load on INT_LDO
CINT_LDO = 1 µF, see Table 9-3.
150ms
COUTNominal output capacitor valueCeramic, X5R or X7R, see Table 9-3.0.1122µF
ToleranceCeramic, X5R or X7R, rated voltage ≥ 6.3 V–20%20%
DCDC1 (1.1-V BUCK)
VIN_DCDC1Input voltage rangeVIN_BIAS > VUVLO5.5V
VDCDC1Output voltage rangeAdjustable through I2C0.851.675V
DC accuracy2.7 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A–2%2%
IOUTContinuous output currentVIN_DCDC1 > 2.7 V1.8A
IQQuiescent currentTotal current from IN_DCDC1 pin; Device not switching, no load2550µA
RDS(ON)High-side FET on resistanceVIN_DCDC1 = 3.6 V230355
Low-side FET on resistanceVIN_DCDC1 = 3.6 V90145
ILIMITHigh-side current limitVIN_DCDC1 = 3.6 V2.8A
Low-side current limitVIN_DCDC1 = 3.6 V3.1
VPGPower-good thresholdVOUT fallingSTRICT = 0b88.5%90%91.5%
STRICT = 1b96%96.5%97%
HysteresisVOUT risingSTRICT = 0b3.8%4.1%4.4%
STRICT = 1b0.25%
DeglitchVOUT fallingSTRICT = 0b1ms
STRICT = 1b50µs
VOUT risingSTRICT = 0b10µs
STRICT = 1b10µs
Time-out5ms
VOVOvervoltage detection thresholdVOUT rising, STRICT = 1b103%103.5%104%
HysteresisVOUT falling, STRICT = 1b0.25%
DeglitchVOUT rising, STRICT = 1b50µs
IINRUSHInrush currentVIN_DCDC1 = 3.6 V; COUT = 10 µF to 100 µF500mA
RDISDischarge resistor150250350Ω
LNominal inductor valueSee Table 9-2.11.52.2µH
Tolerance–30%30%
COUTOutput capacitance valueCeramic, X5R or X7R, see Table 9-3.1022100(8)µF
DCDC2 (1.1-V BUCK)
VIN_DCDC2Input voltage rangeVIN_BIAS > VUVLO2.75.5V
VDCDC2Output voltage rangeAdjustable through I2C0.851.675V
DC accuracy2.7 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A–2%2%
IOUTContinuous output currentVIN_DCDC2 > 2.7 V1.8A
IQQuiescent currentTotal current from IN_DCDC2 pin; device not switching, no load2550µA
RDS(ON)High-side FET on resistanceVIN_DCDC2 = 3.6 V230355
Low-side FET on resistanceVIN_DCDC2 = 3.6 V90145
ILIMITHigh-side current limitVIN_DCDC2 = 3.6 V2.8A
Low-side current limitVIN_DCDC2 = 3.6 V3.1
VPGPower-good thresholdVOUT fallingSTRICT = 0b88.5%90%91.5%
STRICT = 1b96%96.5%97%
HysteresisVOUT risingSTRICT = 0b3.8%4.1%4.4%
STRICT = 1b0.25%
DeglitchVOUT fallingSTRICT = 0b1ms
STRICT = 1b50µs
VOUT risingSTRICT = 0b10µs
STRICT = 1b10µs
Time-outOccurs at enable of DCDC2 and after DCDC2 register write (register 0x17).5ms
VOVOvervoltage detection thresholdVOUT rising, STRICT = 1b103%103.5%104%
HysteresisVOUT falling, STRICT = 1b0.25%
DeglitchVOUT rising, STRICT = 1b50µs
IINRUSHInrush currentVIN_DCDC2 = 3.6 V; COUT = 10 µF to 100 µF500mA
RDISDischarge resistor150250350Ω
LNominal inductor valueSee Table 9-2.11.52.2µH
Tolerance–30%30%
COUTOutput capacitance valueCeramic, X5R or X7R, see Table 9-3.1022100(8)µF
DCDC3 (1.2-V BUCK)
VIN_DCDC3Input voltage rangeVIN_BIAS > VUVLO2.75.5V
VDCDC3Output voltage rangeAdjustable through I2C0.93.4V
DC accuracy2.7 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A,
VIN_DCDC3 ≥ (VDCDC3 + 700 mV)
–2%2%
IOUTContinuous output currentVIN_DCDC3 > 2.7 V1.8A
IQQuiescent currentTotal current from IN_DCDC3 pin;
Device not switching, no load
2550µA
RDS(ON)High-side FET on resistanceVIN_DCDC3 = 3.6 V230345
Low-side FET on resistanceVIN_DCDC3 = 3.6 V100150
ILIMITHigh-side current limitVIN_DCDC3 = 3.6 V2.8A
Low-side current limitVIN_DCDC3 = 3.6 V3
VPGPower-good thresholdVOUT fallingSTRICT = 0b88.5%90%91.5%
STRICT = 1b95%95.5%96%
HysteresisVOUT risingSTRICT = 0b3.8%4.1%4.4%
STRICT = 1b0.25%
DeglitchVOUT fallingSTRICT = 0b1ms
STRICT = 1b50µs
VOUT risingSTRICT = 0b10µs
STRICT = 1b10µs
Time-outOccurs at enable of DCDC3 and after DCDC3 register write (register 0x18).5ms
VOVOvervoltage detection thresholdVOUT rising, STRICT = 1b104%104.5%105%
HysteresisVOUT falling, STRICT = 1b0.25%
DeglitchVOUT rising, STRICT = 1b50µs
IINRUSHInrush currentVIN_DCDC3 = 3.6 V; COUT = 10 µF to 100 µF500mA
RDISDischarge resistor150250350Ω
LNominal inductor valueSee Table 9-2.1.01.52.2µH
Tolerance–30%30%
COUTOutput capacitance valueCeramic, X5R or X7R, see Table 9-3.1022100µF
DCDC4 (3.3-V BUCK-BOOST) / ANALOG AND I/O
Output voltage ripplePFM mode enabled;
4.2 V ≤ VIN ≤ 5.5 V;
0 A ≤ IOUT1.6 A
VOUT = 3.3 V
150mVpp
Minimum duty cycle in step-down mode18%
IOUTContinuous output currentVIN_DCDC4 = 2.8 V, VOUT = 3.3 V1A
VIN_DCDC4 = 3.6 V, VOUT = 3.3 V1.3
VIN_DCDC4 = 5 V, VOUT = 3.3 V1.6
IQQuiescent currentTotal current from IN_DCDC4 pin; Device not switching, no load.2550µA
fSWSwitching frequency2400kHz
RDS(ON)High-side FET on resistanceVIN_DCDC3 = 3.6 VIN_DCDC4 to L4A166
L4B to DCDC4149
Low-side FET on resistanceVIN_DCDC3 = 3.6 VL4A to GND142190
L4B to GND144190
ILIMITAverage switch current limitVIN_DCDC4 = 3.6 V3000mA
VPGPower-good thresholdVOUT fallingSTRICT = 0b88.5%90%91.5%
STRICT = 1b95%95.5%96%
HysteresisVOUT risingSTRICT = 0b3.8%4.1%4.4%
STRICT = 1b0.25%
DeglitchVOUT fallingSTRICT = 0b1ms
STRICT = 1b50µs
VOUT risingSTRICT = 0b10µs
STRICT = 1b10µs
Time-outOccurs at enable of DCDC4 and after DCDC4 register write (register 0x19)5ms
VOVOvervoltage detection thresholdVOUT rising, STRICT = 1b104%104.5%105%
HysteresisVOUT falling, STRICT = 1b0.25%
DeglitchVOUT rising, STRICT = 1b50µs
IINRUSHInrush currentVIN_DCDC4 = 3.3 V ≤ VINDCDC4 ≤ 5.5 V; 40 µF ≤ COUT ≤ 100 µF500mA
RDISDischarge resistor150250350Ω
LNominal inductor valueSee Table 9-2.1.21.52.2µH
Tolerance–30%30%
COUTOutput capacitance valueCeramic, X5R or X7R, see Table 9-3.4080100µF
DCDC5 and DCDC6 POWER PATH
VCCDCDC5 and DCDC6 input voltage range.VIN_BU = 0 V2.23.3V
VIN_BUDCDC5 and DCDC6 input voltage range(1)2.25.5V
tRISEVCC, VIN_BU rise timeVCC = 0 V to 3.3 V, VIN_BU = 0 V to 5.5 V30µs
RDS(ON)Power path switch impedanceCC to SYS_BU
VCC = 2.4 V, VIN_BU = 0 V
14.5Ω
Power path switch impedanceIN_BU to SYS_BU
VIN_BU = 3.6 V
10.5
ILEAKForward leakage currentInto CC pin;
VCC = 3.3 V, VIN_BU = 0 V;
OFF state; FSEAL = 0b;
over full temperature range
50300nA
Reverse leakage currentOut of CC pin;
VCC = 1.5 V; VIN_BU = 5.5 V;
over full temperature range
500
RCCAcceptable CC source impedanceIOUT, DCDC5 < 10 µA;
IOUT, DCDC6 < 10 µA
1000Ω
IQQuiescent currentAverage current into CC pin; RECOVERY or OFF state; VIN_BU = 0 V; VCC = 2.4 V; DCDC5 and DCDC6 enabled, no load TJ = 25°C350nA
QINRUSHInrush chargeVIN_BIAS = decaying; CC = 3 V; CSYS_BU = 1 µF; SYS_BU = 2.3 V to 3 V; CCseries_resist = 10 Ω CCC = 4.7 µF720nC
DCDC5 (1-V BATTERY BACKUP SUPPLY)
VDCDC5Output voltage1V
DC accuracy2.7 V ≤ VIN_BU ≤ 5.5 V;
1.5 µA ≤ IOUT ≤ 25 mA
–40°C ≤ TA < 0°C
–2.5%2.5%
2.7 V ≤ VIN_BU ≤ 5.5 V
1.5 µA ≤ IOUT ≤ 25 mA
0°C ≤ TA < 105°C
–2%2%
2.2 V ≤ VCC ≤ 3.3 V; VIN_BU = 0;
1.5 µA ≤ IOUT ≤ 100 µA
–2.5%2.5%
Output voltage rippleL = 10 µH; COUT = 22 µF; 100-µA load, occurs during band-gap sampling32(9)mVpp
IOUTContinuous output current2.2 V ≤ VCC ≤ 3.3 V
VIN_BU = 0 V
10100µA
2.7 V ≤ VIN_BU ≤ 5.5 V25mA
RDS(ON)High-side FET on resistanceVIN_BU = 2.8 V2.53.5Ω
Low-side FET on resistanceVIN_BU = 2.8 V23
ILIMITHigh-side current limitVIN_BU = 2.8 V50mA
VPGPower-good thresholdVOUT falling79%85%91%
HysteresisVOUT rising6%
LNominal inductor valueChip inductor, see Table 9-3.4.71022µH
Tolerance–30%30%
COUTOutput capacitance valueCeramic, X5R or X7R, see Table 9-3.20(10)47µF
Tolerance–20%20%
DCDC6 (1.8-V BATTERY BACKUP SUPPLY)
VDCDC6Output voltage1.8V
VDCDC6Output voltage rippleL = 10 µH; COUT = 22 µF; 100-µA load30(9)mVpp
IOUTContinuous output current2.2 V ≤ VCC ≤ 3.3 V
VIN_BU = 0 V
10100µA
2.7 V ≤ VIN_BU ≤ 5.5 V25mA
RDS(ON)High-side FET on resistanceVIN_BU = 3 V2.53.5Ω
Low-side FET on resistanceVIN_BU = 3 V23
ILIMITHigh-side current limitVIN_BU = 3 V50mA
VPGPower-good thresholdVOUT falling87%91%95%
HysteresisVOUT rising3%
LNominal inductor valueChip inductor, see Table 9-34.71022µH
Tolerance–30%30%
COUTOutput capacitance valueCeramic, X5R or X7R, see Table 9-320(10)47µF
Tolerance–20%20%
LDO1 (1.8-V LDO)
VIN_LDO1Input voltage rangeVIN_BIAS > VUVLO1.85.5V
IQQuiescent currentNo load35µA
VOUTOutput voltage rangeAdjustable through I2C0.93.4V
DC accuracyVOUT + 0.2 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 200 mA–2%2%
IOUTOutput current rangeVIN_LDO1 – VDO = VOUT0200mA
VIN_LDO1 > 2.7 V, VOUT = 1.8 V0400
ILIMITShort circuit current limitOutput shorted to GND445550mA
VDODropout voltageIOUT = 100 mA, VIN = 3.6 V200mV
VPGPower-good thresholdVOUT fallingSTRICT = 0b86%90%94%
STRICT = 1b95%95.5%96%
Hysteresis, VOUT risingSTRICT = 0b3%4%5%
STRICT = 1b0.25%
DeglitchVOUT fallingSTRICT = 0b1ms
STRICT = 1b50µs
VOUT risingSTRICT = 0b10µs
STRICT = 1b10µs
Time-outOccurs at enable of LDO and after LDO register write (register 0x1B)5ms
VOVOvervoltage detection thresholdVOUT rising, STRICT = 1b104%104.5%105%
HysteresisVOUT falling, STRICT = 1b0.25%
DeglitchVOUT rising, STRICT = 1b50µs
VOUT falling, STRICT = 1b1ms
RDISDischarge resistor150250380Ω
COUTOutput capacitance valueCeramic, X5R or X7R22100µF
LOAD SWITCH 1 (LS1)
VIN_LS1Input voltage rangeVIN_BIAS > VUVLO1.23.6V
RDS(ON)Static on resistanceVIN_LS1 = 3.3 V, IOUT = 300 mA, over full temperature range110
VIN_LS1 = 1.8 V, IOUT = 300 mA,
DDR2, LPDDR, MDDR at 266 MHz over full temperature range
110
VIN_LS1 = 1.5 V, IOUT = 300 mA,
DDR3 at 333 MHz over full temperature range
110
VIN_LS1 = 1.35 V, IOUT = 300 mA,
DDR3L at 333 MHz over full temperature range
110
VIN_LS1 = 1.2 V, IOUT = 200 mA,
LPDDR2 at 333 MHz over full temperature range
150
ILIMITShort circuit current limitOutput shorted to GND350mA
tBLANKInterrupt blanking timeOutput shorted to GND until interrupt is triggered.15ms
RDISInternal discharge resistor at output(2)LS1DCHRG = 1150250380Ω
TOTSOvertemperature shutdown(3)125132139°C
Hysteresis10
COUTNominal output capacitance valueCeramic, X5R or X7R, see Table 9-3.10100µF
LOAD SWITCH 2 (LS2)
VIN_LS2Input voltage rangeVIN_BIAS > VUVLO35.5V
VUVLOUndervoltage lockoutMeasured at IN_LS2. Supply falling(4)2.482.62.7V
HysteresisInput voltage rising170mV
RDS(ON)Static on resistanceVIN_LS2 = 5 V, IOUT = 500 mA, over full temperature range500
ILIMITShort circuit current limitOutput shorted to GND; VIN_LS2 ≥ 4 VLS2ILIM[1:0] = 00b94126mA
LS2ILIM[1:0] = 01b188251
LS2ILIM[1:0] = 10b465631
LS2ILIM[1:0] = 11b9221290
ILEAKReverse leakage currentVLS2 > VIN_LS2 + 1 V1230µA
tBLANKInterrupt blanking timeOutput shorted to GND until interrupt is triggered15ms
RDISInternal discharge resistor at output(2)LS2DCHRG = 1b150250380Ω
TOTSOvertemperature shutdown(4)125132139°C
Hysteresis10
COUTNominal output capacitance valueCeramic, X5R or X7R, see Table 9-3.1100µF
LOAD SWITCH 3 (LS3)
VIN_LS3Input voltage rangeVIN_BIAS > VUVLO1.810V
RDS(ON)Static on resistanceVIN_LS3 = 9 V, IOUT= 500 mA, over full temperature range440
VIN_LS3 = 5 V, IOUT= 500 mA, over full temperature range526
VIN_LS3 = 2.8 V, IOUT= 200 mA, over full temperature range656
VIN_LS3 = 1.8 V, IOUT= 200 mA, over full temperature range910
ILIMITShort circuit current limitVIN_LS3 > 2.3 V,
Output shorted to GND
LS3ILIM[1:0] = 00b98126mA
LS3ILIM[1:0] = 01b194253
LS3ILIM[1:0] = 10b475738
LS3ILIM[1:0] = 11b9001234
VIN_LS3 ≤ 2.3 V,
Output shorted to GND
LS3ILIM[1:0] = 00b98126
LS3ILIM[1:0] = 01b194253
LS3ILIM[1:0] = 10b475738
tBLANKInterrupt blanking timeOutput shorted to GND until interrupt is triggered.15ms
RDISInternal discharge resistor at output(2)LS3DCHRG = 165010001500Ω
TOTSOvertemperature shutdown(4)125132139°C
Hysteresis10°C
COUTNominal output capacitance valueCeramic, X5R or X7R, see Table 9-3.1100220µF
BACKUP BATTERY MONITOR
VTHComparator thresholdIdeal level3V
Good level2.6V
Low level2.3V
Accuracy–3%3%
RLOADLoad impedanceApplied from CC to GND during comparison.70100130
tDLYMeasurement delayRLOAD is connected during delay time. Measurement is taken at the end of delay.600ms
I/O LEVELS AND TIMING CHARACTERISTICS
PGDLYPGOOD delay timePGDLY[1:0] = 00b10ms
PGDLY[1:0] = 01b20
PGDLY[1:0] = 10b50
PGDLY[1:0] = 11b150
tDGDeglitch timePB inputRising edge100ms
Falling edge50ms
AC_DET inputRising edge100µs
Falling edge10ms
PWR_EN inputRising edge10ms
Falling edge100µs
GPIO1Rising edge1ms
Falling edge1ms
GPIO3Rising edge5µs
Falling edge5µs
tRESETReset timePB input held lowTRST = 0b8s
TRST = 1b15
VIHHigh level input voltageSCL, SDA, GPIO1, and GPIO31.3V
AC_DET, PB0.66 × IN_BIAS
PWR_EN1.3
VILLow level input voltageSCL, SDA, PWR_EN, AC_DET, PB, GPIO1, and GPIO300.4V
VOHHigh level output voltageGPO2; ISOURCE = 5 mA; GPO2_BUF = 1VIN_LS1 – 0.3VIN_LS1V
PGOOD_BU; ISOURCE = 100 µAVDCDC6 – 10 mV
VOLLow level output voltagenWAKEUP, nINT, SDA, PGOOD, GPIO1, GPO2, and GPIO3; ISINK = 2 mA00.3V
nPFO; ISINK = 2 mA00.35
PGOOD_BU; ISINK = 100 µA00.3
VPFIPower-fail comparator thresholdInput falling800mV
HysteresisInput rising40mV
Accuracy–4%4%
DeglitchInput falling25µs
Input rising10ms
IDC34_SELDC34_SEL bias currentEnabled only at power-up.9.051011.93µA
VDC34_SELDCDC3 and DCDC4 power-up default selection thresholdsThreshold 1100mV
Threshold 2163
Threshold 3275
Threshold 4400
Threshold 5575
Threshold 6825
Threshold 71200
RDC34_SELDCDC3 and DCDC4 power-up default selection resistor valuesSetting 0007.7
Setting 111.812.112.4
Setting 219.52020.5
Setting 330.931.632.3
Setting 444.445.346.3
Setting 564.866.167.3
Setting 693.695.397.2
Setting 7146150
IBIASInput bias currentSCL, SDA, GPIO1(5), GPIO3(5); VIN = 3.3 V0.011µA
PB, AC_DET, PFI; VIN = 3.3 V500nA
ILEAKPin leakage currentnINT, nWAKEUP, nPFO, PGOOD, PWR_EN, GPIO1(6), GPO2(7), GPIO3(6)
VOUT = 3.3 V
500nA
OSCILLATOR
ƒOSCOscillator frequency2400kHz
Frequency accuracyTJ = –40°C to +105°C–12%12%
OVERTEMPERATURE SHUTDOWN
TOTSOvertemperature shutdownIncreasing junction temperature135145155°C
HysteresisDecreasing junction temperature20
TWARNHigh-temperature warningIncreasing junction temperature90100110°C
HysteresisDecreasing junction temperature15
IN_BU has priority over CC input.
Discharge function disabled by default.
Switch is temporarily turned OFF if temperature exceeds OTS threshold.
Switch is temporarily turned OFF if input voltage drops below UVLO threshold.
Configured as input.
Configured as output.
Configured as open-drain output.
500-µF of remote capacitance can be supported for DCDC1 and DCDC2.
For PHP package: 160 mVpp at -40°C, and 120 mVpp from 25°C to 105°C.
For PHP package: 40 µF.