JAJSI26A November 2019 – February 2021 TPS6521815
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
INPUT VOLTAGE AND CURRENTS | |||||||
VIN_BIAS | Input supply voltage range | Normal operation | 2.7 | 5.5 | V | ||
EEPROM programming | 4.5 | 5.5 | |||||
Deglitch time | 5 | ms | |||||
IOFF | OFF state current, total current into IN_BIAS, IN_DCDCx, IN_LDO1, IN_LS | VIN = 3.6 V; All rails disabled. TJ = 0°C to 85°C | 5 | µA | |||
ISUSPEND | SUSPEND current, total current into IN_BIAS, IN_DCDCx, IN_LDO1, IN_LS | VIN = 3.6 V; DCDC3 enabled, low-power mode, no load. All other rails disabled. TJ = 0°C to 105°C | 220 | µA | |||
SYS_BU | |||||||
VSYS_BU | SYS_BU voltage range | Powered from VIN_BU or VCC | 2.2 | 5.5 | V | ||
CSYS_BU | Recommended SYS_BU capacitor | Ceramic, X5R or X7R, see Table 9-3. | 1 | µF | |||
Tolerance | Ceramic, X5R or X7R, rated voltage ≥ 6.3 V | –20% | 20% | ||||
INT_LDO | |||||||
VINT_LDO | Output voltage | 2.5 | V | ||||
DC accuracy | IOUT < 10 mA | –2% | 2% | ||||
IOUT | Output current range | Maximum allowable external load | 0 | 10 | mA | ||
ILIMIT | Short circuit current limit | Output shorted to GND | 23 | mA | |||
tHOLD | Hold-up time | Measured from VINT_LDO = to VINT_LDO = 1.8 V All rails enabled before power off, IN_BIAS tied to IN_DCDC1-4, IN_LDO1 VIN_BIAS = 2.8 V to 0 V in < 5 µs No external load on INT_LDO CINT_LDO = 1 µF, see Table 9-3. | 150 | ms | |||
COUT | Nominal output capacitor value | Ceramic, X5R or X7R, see Table 9-3. | 0.1 | 1 | 22 | µF | |
Tolerance | Ceramic, X5R or X7R, rated voltage ≥ 6.3 V | –20% | 20% | ||||
DCDC1 (1.1-V BUCK) | |||||||
VIN_DCDC1 | Input voltage range | VIN_BIAS > VUVLO | 5.5 | V | |||
VDCDC1 | Output voltage range | Adjustable through I2C | 0.85 | 1.675 | V | ||
DC accuracy | 2.7 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A | –2% | 2% | ||||
IOUT | Continuous output current | VIN_DCDC1 > 2.7 V | 1.8 | A | |||
IQ | Quiescent current | Total current from IN_DCDC1 pin; Device not switching, no load | 25 | 50 | µA | ||
RDS(ON) | High-side FET on resistance | VIN_DCDC1 = 3.6 V | 230 | 355 | mΩ | ||
Low-side FET on resistance | VIN_DCDC1 = 3.6 V | 90 | 145 | ||||
ILIMIT | High-side current limit | VIN_DCDC1 = 3.6 V | 2.8 | A | |||
Low-side current limit | VIN_DCDC1 = 3.6 V | 3.1 | |||||
VPG | Power-good threshold | VOUT falling | STRICT = 0b | 88.5% | 90% | 91.5% | |
STRICT = 1b | 96% | 96.5% | 97% | ||||
Hysteresis | VOUT rising | STRICT = 0b | 3.8% | 4.1% | 4.4% | ||
STRICT = 1b | 0.25% | ||||||
Deglitch | VOUT falling | STRICT = 0b | 1 | ms | |||
STRICT = 1b | 50 | µs | |||||
VOUT rising | STRICT = 0b | 10 | µs | ||||
STRICT = 1b | 10 | µs | |||||
Time-out | 5 | ms | |||||
VOV | Overvoltage detection threshold | VOUT rising, STRICT = 1b | 103% | 103.5% | 104% | ||
Hysteresis | VOUT falling, STRICT = 1b | 0.25% | |||||
Deglitch | VOUT rising, STRICT = 1b | 50 | µs | ||||
IINRUSH | Inrush current | VIN_DCDC1 = 3.6 V; COUT = 10 µF to 100 µF | 500 | mA | |||
RDIS | Discharge resistor | 150 | 250 | 350 | Ω | ||
L | Nominal inductor value | See Table 9-2. | 1 | 1.5 | 2.2 | µH | |
Tolerance | –30% | 30% | |||||
COUT | Output capacitance value | Ceramic, X5R or X7R, see Table 9-3. | 10 | 22 | 100(8) | µF | |
DCDC2 (1.1-V BUCK) | |||||||
VIN_DCDC2 | Input voltage range | VIN_BIAS > VUVLO | 2.7 | 5.5 | V | ||
VDCDC2 | Output voltage range | Adjustable through I2C | 0.85 | 1.675 | V | ||
DC accuracy | 2.7 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A | –2% | 2% | ||||
IOUT | Continuous output current | VIN_DCDC2 > 2.7 V | 1.8 | A | |||
IQ | Quiescent current | Total current from IN_DCDC2 pin; device not switching, no load | 25 | 50 | µA | ||
RDS(ON) | High-side FET on resistance | VIN_DCDC2 = 3.6 V | 230 | 355 | mΩ | ||
Low-side FET on resistance | VIN_DCDC2 = 3.6 V | 90 | 145 | ||||
ILIMIT | High-side current limit | VIN_DCDC2 = 3.6 V | 2.8 | A | |||
Low-side current limit | VIN_DCDC2 = 3.6 V | 3.1 | |||||
VPG | Power-good threshold | VOUT falling | STRICT = 0b | 88.5% | 90% | 91.5% | |
STRICT = 1b | 96% | 96.5% | 97% | ||||
Hysteresis | VOUT rising | STRICT = 0b | 3.8% | 4.1% | 4.4% | ||
STRICT = 1b | 0.25% | ||||||
Deglitch | VOUT falling | STRICT = 0b | 1 | ms | |||
STRICT = 1b | 50 | µs | |||||
VOUT rising | STRICT = 0b | 10 | µs | ||||
STRICT = 1b | 10 | µs | |||||
Time-out | Occurs at enable of DCDC2 and after DCDC2 register write (register 0x17). | 5 | ms | ||||
VOV | Overvoltage detection threshold | VOUT rising, STRICT = 1b | 103% | 103.5% | 104% | ||
Hysteresis | VOUT falling, STRICT = 1b | 0.25% | |||||
Deglitch | VOUT rising, STRICT = 1b | 50 | µs | ||||
IINRUSH | Inrush current | VIN_DCDC2 = 3.6 V; COUT = 10 µF to 100 µF | 500 | mA | |||
RDIS | Discharge resistor | 150 | 250 | 350 | Ω | ||
L | Nominal inductor value | See Table 9-2. | 1 | 1.5 | 2.2 | µH | |
Tolerance | –30% | 30% | |||||
COUT | Output capacitance value | Ceramic, X5R or X7R, see Table 9-3. | 10 | 22 | 100(8) | µF | |
DCDC3 (1.2-V BUCK) | |||||||
VIN_DCDC3 | Input voltage range | VIN_BIAS > VUVLO | 2.7 | 5.5 | V | ||
VDCDC3 | Output voltage range | Adjustable through I2C | 0.9 | 3.4 | V | ||
DC accuracy | 2.7 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A, VIN_DCDC3 ≥ (VDCDC3 + 700 mV) | –2% | 2% | ||||
IOUT | Continuous output current | VIN_DCDC3 > 2.7 V | 1.8 | A | |||
IQ | Quiescent current | Total current from IN_DCDC3 pin; Device not switching, no load | 25 | 50 | µA | ||
RDS(ON) | High-side FET on resistance | VIN_DCDC3 = 3.6 V | 230 | 345 | mΩ | ||
Low-side FET on resistance | VIN_DCDC3 = 3.6 V | 100 | 150 | ||||
ILIMIT | High-side current limit | VIN_DCDC3 = 3.6 V | 2.8 | A | |||
Low-side current limit | VIN_DCDC3 = 3.6 V | 3 | |||||
VPG | Power-good threshold | VOUT falling | STRICT = 0b | 88.5% | 90% | 91.5% | |
STRICT = 1b | 95% | 95.5% | 96% | ||||
Hysteresis | VOUT rising | STRICT = 0b | 3.8% | 4.1% | 4.4% | ||
STRICT = 1b | 0.25% | ||||||
Deglitch | VOUT falling | STRICT = 0b | 1 | ms | |||
STRICT = 1b | 50 | µs | |||||
VOUT rising | STRICT = 0b | 10 | µs | ||||
STRICT = 1b | 10 | µs | |||||
Time-out | Occurs at enable of DCDC3 and after DCDC3 register write (register 0x18). | 5 | ms | ||||
VOV | Overvoltage detection threshold | VOUT rising, STRICT = 1b | 104% | 104.5% | 105% | ||
Hysteresis | VOUT falling, STRICT = 1b | 0.25% | |||||
Deglitch | VOUT rising, STRICT = 1b | 50 | µs | ||||
IINRUSH | Inrush current | VIN_DCDC3 = 3.6 V; COUT = 10 µF to 100 µF | 500 | mA | |||
RDIS | Discharge resistor | 150 | 250 | 350 | Ω | ||
L | Nominal inductor value | See Table 9-2. | 1.0 | 1.5 | 2.2 | µH | |
Tolerance | –30% | 30% | |||||
COUT | Output capacitance value | Ceramic, X5R or X7R, see Table 9-3. | 10 | 22 | 100 | µF | |
DCDC4 (3.3-V BUCK-BOOST) / ANALOG AND I/O | |||||||
Output voltage ripple | PFM mode enabled; 4.2 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.6 A VOUT = 3.3 V | 150 | mVpp | ||||
Minimum duty cycle in step-down mode | 18% | ||||||
IOUT | Continuous output current | VIN_DCDC4 = 2.8 V, VOUT = 3.3 V | 1 | A | |||
VIN_DCDC4 = 3.6 V, VOUT = 3.3 V | 1.3 | ||||||
VIN_DCDC4 = 5 V, VOUT = 3.3 V | 1.6 | ||||||
IQ | Quiescent current | Total current from IN_DCDC4 pin; Device not switching, no load. | 25 | 50 | µA | ||
fSW | Switching frequency | 2400 | kHz | ||||
RDS(ON) | High-side FET on resistance | VIN_DCDC3 = 3.6 V | IN_DCDC4 to L4A | 166 | mΩ | ||
L4B to DCDC4 | 149 | ||||||
Low-side FET on resistance | VIN_DCDC3 = 3.6 V | L4A to GND | 142 | 190 | |||
L4B to GND | 144 | 190 | |||||
ILIMIT | Average switch current limit | VIN_DCDC4 = 3.6 V | 3000 | mA | |||
VPG | Power-good threshold | VOUT falling | STRICT = 0b | 88.5% | 90% | 91.5% | |
STRICT = 1b | 95% | 95.5% | 96% | ||||
Hysteresis | VOUT rising | STRICT = 0b | 3.8% | 4.1% | 4.4% | ||
STRICT = 1b | 0.25% | ||||||
Deglitch | VOUT falling | STRICT = 0b | 1 | ms | |||
STRICT = 1b | 50 | µs | |||||
VOUT rising | STRICT = 0b | 10 | µs | ||||
STRICT = 1b | 10 | µs | |||||
Time-out | Occurs at enable of DCDC4 and after DCDC4 register write (register 0x19) | 5 | ms | ||||
VOV | Overvoltage detection threshold | VOUT rising, STRICT = 1b | 104% | 104.5% | 105% | ||
Hysteresis | VOUT falling, STRICT = 1b | 0.25% | |||||
Deglitch | VOUT rising, STRICT = 1b | 50 | µs | ||||
IINRUSH | Inrush current | VIN_DCDC4 = 3.3 V ≤ VINDCDC4 ≤ 5.5 V; 40 µF ≤ COUT ≤ 100 µF | 500 | mA | |||
RDIS | Discharge resistor | 150 | 250 | 350 | Ω | ||
L | Nominal inductor value | See Table 9-2. | 1.2 | 1.5 | 2.2 | µH | |
Tolerance | –30% | 30% | |||||
COUT | Output capacitance value | Ceramic, X5R or X7R, see Table 9-3. | 40 | 80 | 100 | µF | |
DCDC5 and DCDC6 POWER PATH | |||||||
VCC | DCDC5 and DCDC6 input voltage range. | VIN_BU = 0 V | 2.2 | 3.3 | V | ||
VIN_BU | DCDC5 and DCDC6 input voltage range(1) | 2.2 | 5.5 | V | |||
tRISE | VCC, VIN_BU rise time | VCC = 0 V to 3.3 V, VIN_BU = 0 V to 5.5 V | 30 | µs | |||
RDS(ON) | Power path switch impedance | CC to SYS_BU VCC = 2.4 V, VIN_BU = 0 V | 14.5 | Ω | |||
Power path switch impedance | IN_BU to SYS_BU VIN_BU = 3.6 V | 10.5 | |||||
ILEAK | Forward leakage current | Into CC pin; VCC = 3.3 V, VIN_BU = 0 V; OFF state; FSEAL = 0b; over full temperature range | 50 | 300 | nA | ||
Reverse leakage current | Out of CC pin; VCC = 1.5 V; VIN_BU = 5.5 V; over full temperature range | 500 | |||||
RCC | Acceptable CC source impedance | IOUT, DCDC5 < 10 µA; IOUT, DCDC6 < 10 µA | 1000 | Ω | |||
IQ | Quiescent current | Average current into CC pin; RECOVERY or OFF state; VIN_BU = 0 V; VCC = 2.4 V; DCDC5 and DCDC6 enabled, no load TJ = 25°C | 350 | nA | |||
QINRUSH | Inrush charge | VIN_BIAS = decaying; CC = 3 V; CSYS_BU = 1 µF; SYS_BU = 2.3 V to 3 V; CCseries_resist = 10 Ω CCC = 4.7 µF | 720 | nC | |||
DCDC5 (1-V BATTERY BACKUP SUPPLY) | |||||||
VDCDC5 | Output voltage | 1 | V | ||||
DC accuracy | 2.7 V ≤ VIN_BU ≤ 5.5 V; 1.5 µA ≤ IOUT ≤ 25 mA –40°C ≤ TA < 0°C | –2.5% | 2.5% | ||||
2.7 V ≤ VIN_BU ≤ 5.5 V 1.5 µA ≤ IOUT ≤ 25 mA 0°C ≤ TA < 105°C | –2% | 2% | |||||
2.2 V ≤ VCC ≤ 3.3 V; VIN_BU = 0; 1.5 µA ≤ IOUT ≤ 100 µA | –2.5% | 2.5% | |||||
Output voltage ripple | L = 10 µH; COUT = 22 µF; 100-µA load, occurs during band-gap sampling | 32(9) | mVpp | ||||
IOUT | Continuous output current | 2.2 V ≤ VCC ≤ 3.3 V VIN_BU = 0 V | 10 | 100 | µA | ||
2.7 V ≤ VIN_BU ≤ 5.5 V | 25 | mA | |||||
RDS(ON) | High-side FET on resistance | VIN_BU = 2.8 V | 2.5 | 3.5 | Ω | ||
Low-side FET on resistance | VIN_BU = 2.8 V | 2 | 3 | ||||
ILIMIT | High-side current limit | VIN_BU = 2.8 V | 50 | mA | |||
VPG | Power-good threshold | VOUT falling | 79% | 85% | 91% | ||
Hysteresis | VOUT rising | 6% | |||||
L | Nominal inductor value | Chip inductor, see Table 9-3. | 4.7 | 10 | 22 | µH | |
Tolerance | –30% | 30% | |||||
COUT | Output capacitance value | Ceramic, X5R or X7R, see Table 9-3. | 20(10) | 47 | µF | ||
Tolerance | –20% | 20% | |||||
DCDC6 (1.8-V BATTERY BACKUP SUPPLY) | |||||||
VDCDC6 | Output voltage | 1.8 | V | ||||
VDCDC6 | Output voltage ripple | L = 10 µH; COUT = 22 µF; 100-µA load | 30(9) | mVpp | |||
IOUT | Continuous output current | 2.2 V ≤ VCC ≤ 3.3 V VIN_BU = 0 V | 10 | 100 | µA | ||
2.7 V ≤ VIN_BU ≤ 5.5 V | 25 | mA | |||||
RDS(ON) | High-side FET on resistance | VIN_BU = 3 V | 2.5 | 3.5 | Ω | ||
Low-side FET on resistance | VIN_BU = 3 V | 2 | 3 | ||||
ILIMIT | High-side current limit | VIN_BU = 3 V | 50 | mA | |||
VPG | Power-good threshold | VOUT falling | 87% | 91% | 95% | ||
Hysteresis | VOUT rising | 3% | |||||
L | Nominal inductor value | Chip inductor, see Table 9-3 | 4.7 | 10 | 22 | µH | |
Tolerance | –30% | 30% | |||||
COUT | Output capacitance value | Ceramic, X5R or X7R, see Table 9-3 | 20(10) | 47 | µF | ||
Tolerance | –20% | 20% | |||||
LDO1 (1.8-V LDO) | |||||||
VIN_LDO1 | Input voltage range | VIN_BIAS > VUVLO | 1.8 | 5.5 | V | ||
IQ | Quiescent current | No load | 35 | µA | |||
VOUT | Output voltage range | Adjustable through I2C | 0.9 | 3.4 | V | ||
DC accuracy | VOUT + 0.2 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 200 mA | –2% | 2% | ||||
IOUT | Output current range | VIN_LDO1 – VDO = VOUT | 0 | 200 | mA | ||
VIN_LDO1 > 2.7 V, VOUT = 1.8 V | 0 | 400 | |||||
ILIMIT | Short circuit current limit | Output shorted to GND | 445 | 550 | mA | ||
VDO | Dropout voltage | IOUT = 100 mA, VIN = 3.6 V | 200 | mV | |||
VPG | Power-good threshold | VOUT falling | STRICT = 0b | 86% | 90% | 94% | |
STRICT = 1b | 95% | 95.5% | 96% | ||||
Hysteresis, VOUT rising | STRICT = 0b | 3% | 4% | 5% | |||
STRICT = 1b | 0.25% | ||||||
Deglitch | VOUT falling | STRICT = 0b | 1 | ms | |||
STRICT = 1b | 50 | µs | |||||
VOUT rising | STRICT = 0b | 10 | µs | ||||
STRICT = 1b | 10 | µs | |||||
Time-out | Occurs at enable of LDO and after LDO register write (register 0x1B) | 5 | ms | ||||
VOV | Overvoltage detection threshold | VOUT rising, STRICT = 1b | 104% | 104.5% | 105% | ||
Hysteresis | VOUT falling, STRICT = 1b | 0.25% | |||||
Deglitch | VOUT rising, STRICT = 1b | 50 | µs | ||||
VOUT falling, STRICT = 1b | 1 | ms | |||||
RDIS | Discharge resistor | 150 | 250 | 380 | Ω | ||
COUT | Output capacitance value | Ceramic, X5R or X7R | 22 | 100 | µF | ||
LOAD SWITCH 1 (LS1) | |||||||
VIN_LS1 | Input voltage range | VIN_BIAS > VUVLO | 1.2 | 3.6 | V | ||
RDS(ON) | Static on resistance | VIN_LS1 = 3.3 V, IOUT = 300 mA, over full temperature range | 110 | mΩ | |||
VIN_LS1 = 1.8 V, IOUT = 300 mA, DDR2, LPDDR, MDDR at 266 MHz over full temperature range | 110 | ||||||
VIN_LS1 = 1.5 V, IOUT = 300 mA, DDR3 at 333 MHz over full temperature range | 110 | ||||||
VIN_LS1 = 1.35 V, IOUT = 300 mA, DDR3L at 333 MHz over full temperature range | 110 | ||||||
VIN_LS1 = 1.2 V, IOUT = 200 mA, LPDDR2 at 333 MHz over full temperature range | 150 | ||||||
ILIMIT | Short circuit current limit | Output shorted to GND | 350 | mA | |||
tBLANK | Interrupt blanking time | Output shorted to GND until interrupt is triggered. | 15 | ms | |||
RDIS | Internal discharge resistor at output(2) | LS1DCHRG = 1 | 150 | 250 | 380 | Ω | |
TOTS | Overtemperature shutdown(3) | 125 | 132 | 139 | °C | ||
Hysteresis | 10 | ||||||
COUT | Nominal output capacitance value | Ceramic, X5R or X7R, see Table 9-3. | 10 | 100 | µF | ||
LOAD SWITCH 2 (LS2) | |||||||
VIN_LS2 | Input voltage range | VIN_BIAS > VUVLO | 3 | 5.5 | V | ||
VUVLO | Undervoltage lockout | Measured at IN_LS2. Supply falling(4) | 2.48 | 2.6 | 2.7 | V | |
Hysteresis | Input voltage rising | 170 | mV | ||||
RDS(ON) | Static on resistance | VIN_LS2 = 5 V, IOUT = 500 mA, over full temperature range | 500 | mΩ | |||
ILIMIT | Short circuit current limit | Output shorted to GND; VIN_LS2 ≥ 4 V | LS2ILIM[1:0] = 00b | 94 | 126 | mA | |
LS2ILIM[1:0] = 01b | 188 | 251 | |||||
LS2ILIM[1:0] = 10b | 465 | 631 | |||||
LS2ILIM[1:0] = 11b | 922 | 1290 | |||||
ILEAK | Reverse leakage current | VLS2 > VIN_LS2 + 1 V | 12 | 30 | µA | ||
tBLANK | Interrupt blanking time | Output shorted to GND until interrupt is triggered | 15 | ms | |||
RDIS | Internal discharge resistor at output(2) | LS2DCHRG = 1b | 150 | 250 | 380 | Ω | |
TOTS | Overtemperature shutdown(4) | 125 | 132 | 139 | °C | ||
Hysteresis | 10 | ||||||
COUT | Nominal output capacitance value | Ceramic, X5R or X7R, see Table 9-3. | 1 | 100 | µF | ||
LOAD SWITCH 3 (LS3) | |||||||
VIN_LS3 | Input voltage range | VIN_BIAS > VUVLO | 1.8 | 10 | V | ||
RDS(ON) | Static on resistance | VIN_LS3 = 9 V, IOUT= 500 mA, over full temperature range | 440 | mΩ | |||
VIN_LS3 = 5 V, IOUT= 500 mA, over full temperature range | 526 | ||||||
VIN_LS3 = 2.8 V, IOUT= 200 mA, over full temperature range | 656 | ||||||
VIN_LS3 = 1.8 V, IOUT= 200 mA, over full temperature range | 910 | ||||||
ILIMIT | Short circuit current limit | VIN_LS3 > 2.3 V, Output shorted to GND | LS3ILIM[1:0] = 00b | 98 | 126 | mA | |
LS3ILIM[1:0] = 01b | 194 | 253 | |||||
LS3ILIM[1:0] = 10b | 475 | 738 | |||||
LS3ILIM[1:0] = 11b | 900 | 1234 | |||||
VIN_LS3 ≤ 2.3 V, Output shorted to GND | LS3ILIM[1:0] = 00b | 98 | 126 | ||||
LS3ILIM[1:0] = 01b | 194 | 253 | |||||
LS3ILIM[1:0] = 10b | 475 | 738 | |||||
tBLANK | Interrupt blanking time | Output shorted to GND until interrupt is triggered. | 15 | ms | |||
RDIS | Internal discharge resistor at output(2) | LS3DCHRG = 1 | 650 | 1000 | 1500 | Ω | |
TOTS | Overtemperature shutdown(4) | 125 | 132 | 139 | °C | ||
Hysteresis | 10 | °C | |||||
COUT | Nominal output capacitance value | Ceramic, X5R or X7R, see Table 9-3. | 1 | 100 | 220 | µF | |
BACKUP BATTERY MONITOR | |||||||
VTH | Comparator threshold | Ideal level | 3 | V | |||
Good level | 2.6 | V | |||||
Low level | 2.3 | V | |||||
Accuracy | –3% | 3% | |||||
RLOAD | Load impedance | Applied from CC to GND during comparison. | 70 | 100 | 130 | kΩ | |
tDLY | Measurement delay | RLOAD is connected during delay time. Measurement is taken at the end of delay. | 600 | ms | |||
I/O LEVELS AND TIMING CHARACTERISTICS | |||||||
PGDLY | PGOOD delay time | PGDLY[1:0] = 00b | 10 | ms | |||
PGDLY[1:0] = 01b | 20 | ||||||
PGDLY[1:0] = 10b | 50 | ||||||
PGDLY[1:0] = 11b | 150 | ||||||
tDG | Deglitch time | PB input | Rising edge | 100 | ms | ||
Falling edge | 50 | ms | |||||
AC_DET input | Rising edge | 100 | µs | ||||
Falling edge | 10 | ms | |||||
PWR_EN input | Rising edge | 10 | ms | ||||
Falling edge | 100 | µs | |||||
GPIO1 | Rising edge | 1 | ms | ||||
Falling edge | 1 | ms | |||||
GPIO3 | Rising edge | 5 | µs | ||||
Falling edge | 5 | µs | |||||
tRESET | Reset time | PB input held low | TRST = 0b | 8 | s | ||
TRST = 1b | 15 | ||||||
VIH | High level input voltage | SCL, SDA, GPIO1, and GPIO3 | 1.3 | V | |||
AC_DET, PB | 0.66 × IN_BIAS | ||||||
PWR_EN | 1.3 | ||||||
VIL | Low level input voltage | SCL, SDA, PWR_EN, AC_DET, PB, GPIO1, and GPIO3 | 0 | 0.4 | V | ||
VOH | High level output voltage | GPO2; ISOURCE = 5 mA; GPO2_BUF = 1 | VIN_LS1 – 0.3 | VIN_LS1 | V | ||
PGOOD_BU; ISOURCE = 100 µA | VDCDC6 – 10 mV | ||||||
VOL | Low level output voltage | nWAKEUP, nINT, SDA, PGOOD, GPIO1, GPO2, and GPIO3; ISINK = 2 mA | 0 | 0.3 | V | ||
nPFO; ISINK = 2 mA | 0 | 0.35 | |||||
PGOOD_BU; ISINK = 100 µA | 0 | 0.3 | |||||
VPFI | Power-fail comparator threshold | Input falling | 800 | mV | |||
Hysteresis | Input rising | 40 | mV | ||||
Accuracy | –4% | 4% | |||||
Deglitch | Input falling | 25 | µs | ||||
Input rising | 10 | ms | |||||
IDC34_SEL | DC34_SEL bias current | Enabled only at power-up. | 9.05 | 10 | 11.93 | µA | |
VDC34_SEL | DCDC3 and DCDC4 power-up default selection thresholds | Threshold 1 | 100 | mV | |||
Threshold 2 | 163 | ||||||
Threshold 3 | 275 | ||||||
Threshold 4 | 400 | ||||||
Threshold 5 | 575 | ||||||
Threshold 6 | 825 | ||||||
Threshold 7 | 1200 | ||||||
RDC34_SEL | DCDC3 and DCDC4 power-up default selection resistor values | Setting 0 | 0 | 0 | 7.7 | kΩ | |
Setting 1 | 11.8 | 12.1 | 12.4 | ||||
Setting 2 | 19.5 | 20 | 20.5 | ||||
Setting 3 | 30.9 | 31.6 | 32.3 | ||||
Setting 4 | 44.4 | 45.3 | 46.3 | ||||
Setting 5 | 64.8 | 66.1 | 67.3 | ||||
Setting 6 | 93.6 | 95.3 | 97.2 | ||||
Setting 7 | 146 | 150 | |||||
IBIAS | Input bias current | SCL, SDA, GPIO1(5), GPIO3(5); VIN = 3.3 V | 0.01 | 1 | µA | ||
PB, AC_DET, PFI; VIN = 3.3 V | 500 | nA | |||||
ILEAK | Pin leakage current | nINT, nWAKEUP, nPFO, PGOOD, PWR_EN, GPIO1(6), GPO2(7), GPIO3(6) VOUT = 3.3 V | 500 | nA | |||
OSCILLATOR | |||||||
ƒOSC | Oscillator frequency | 2400 | kHz | ||||
Frequency accuracy | TJ = –40°C to +105°C | –12% | 12% | ||||
OVERTEMPERATURE SHUTDOWN | |||||||
TOTS | Overtemperature shutdown | Increasing junction temperature | 135 | 145 | 155 | °C | |
Hysteresis | Decreasing junction temperature | 20 | |||||
TWARN | High-temperature warning | Increasing junction temperature | 90 | 100 | 110 | °C | |
Hysteresis | Decreasing junction temperature | 15 |