JAJSLJ7A May   2021  – August 2021 TPS6521855

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     4
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Wake-Up and Power-Up and Power-Down Sequencing
        1. 7.3.1.1  Power-Up Sequencing
        2. 7.3.1.2  Power-Down Sequencing
        3. 7.3.1.3  Strobe 1 and Strobe 2
        4. 7.3.1.4  Supply Voltage Supervisor and Power-Good (PGOOD)
        5. 7.3.1.5  Internal LDO (INT_LDO)
        6. 7.3.1.6  Current Limited Load Switches
          1. 7.3.1.6.1 Load Switch 1 (LS1)
          2. 7.3.1.6.2 Load Switch 2 (LS2)
          3. 7.3.1.6.3 Load Switch 3 (LS3)
        7. 7.3.1.7  LDO1
        8. 7.3.1.8  UVLO
        9. 7.3.1.9  Power-Fail Comparator
        10. 7.3.1.10 DCDC3 and DCDC4 Power-Up Default Selection
        11. 7.3.1.11 I/O Configuration
          1. 7.3.1.11.1 Using GPIO3 as Reset Signal to DCDC1 and DCDC2
        12. 7.3.1.12 Push Button Input (PB)
          1. 7.3.1.12.1 Signaling PB-Low Event on the nWAKEUP Pin
          2. 7.3.1.12.2 Push Button Reset
        13. 7.3.1.13 AC_DET Input (AC_DET)
        14. 7.3.1.14 Interrupt Pin (INT)
        15. 7.3.1.15 I2C Bus Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
      2. 7.4.2 OFF
      3. 7.4.3 ACTIVE
      4. 7.4.4 SUSPEND
      5. 7.4.5 RESET
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Applications Without Backup Battery
      2. 8.1.2 Applications Without Battery Backup Supplies
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Filter Design
        2. 8.2.2.2 Inductor Selection for Buck Converters
        3. 8.2.2.3 Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.1.8 UVLO

Depending on the slew rate of the input voltage into the IN_BIAS pin, the power rails of TPS6521855 will be enabled at either VULVO or VULVO + VHYS.

If the slew rate of the IN_BIAS voltage is greater than 30 V/s, then TPS6521855 will power up at VULVO. Once the input voltage rises above this level, the input voltage may drop to the VUVLO level before the PMIC shuts down. In this scenario, if the input voltage were to fall below VUVLO but above 2.55 V, the input voltage would have to recover above VUVLO in less than 5 ms for the device to remain active.

If the slew rate of the IN_BIAS voltage is less than 30 V/s, then TPS6521855 will power up at VULVO + VHYS. Once the input voltage rises above this level, the input voltage may drop to the VUVLO level before the PMIC shuts down. In this scenario, if the input voltage were to fall below VUVLO but above 2.5 V, the input voltage would have to recover above VUVLO + VHYS in less than 5 ms for the device to remain active.

In either slew rate scenario, if the input voltage were to fall below 2.5 V, the digital core is reset and all remaining power rails are shut down instantaneously and are pulled low to ground by their internal discharge circuitry (DCDC1-4 and LDO1).

GUID-14936B47-645D-45DC-8291-178666671066-low.gif Figure 7-13 Definition of UVLO and Hysteresis

After the UVLO triggers, the internal LDO blocks current flow from its output capacitor back to the IN_BIAS pin, allowing the digital core and the discharge circuits to remain powered for a limited amount of time to properly shut-down and discharge the output rails. The hold-up time is determined by the value of the capacitor connected to INT_LDO. See Section 7.3.1.5 for more details.