JAJSLJ7A May   2021  – August 2021 TPS6521855

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     4
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Wake-Up and Power-Up and Power-Down Sequencing
        1. 7.3.1.1  Power-Up Sequencing
        2. 7.3.1.2  Power-Down Sequencing
        3. 7.3.1.3  Strobe 1 and Strobe 2
        4. 7.3.1.4  Supply Voltage Supervisor and Power-Good (PGOOD)
        5. 7.3.1.5  Internal LDO (INT_LDO)
        6. 7.3.1.6  Current Limited Load Switches
          1. 7.3.1.6.1 Load Switch 1 (LS1)
          2. 7.3.1.6.2 Load Switch 2 (LS2)
          3. 7.3.1.6.3 Load Switch 3 (LS3)
        7. 7.3.1.7  LDO1
        8. 7.3.1.8  UVLO
        9. 7.3.1.9  Power-Fail Comparator
        10. 7.3.1.10 DCDC3 and DCDC4 Power-Up Default Selection
        11. 7.3.1.11 I/O Configuration
          1. 7.3.1.11.1 Using GPIO3 as Reset Signal to DCDC1 and DCDC2
        12. 7.3.1.12 Push Button Input (PB)
          1. 7.3.1.12.1 Signaling PB-Low Event on the nWAKEUP Pin
          2. 7.3.1.12.2 Push Button Reset
        13. 7.3.1.13 AC_DET Input (AC_DET)
        14. 7.3.1.14 Interrupt Pin (INT)
        15. 7.3.1.15 I2C Bus Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
      2. 7.4.2 OFF
      3. 7.4.3 ACTIVE
      4. 7.4.4 SUSPEND
      5. 7.4.5 RESET
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Applications Without Backup Battery
      2. 8.1.2 Applications Without Battery Backup Supplies
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Filter Design
        2. 8.2.2.2 Inductor Selection for Buck Converters
        3. 8.2.2.3 Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.1.4 Supply Voltage Supervisor and Power-Good (PGOOD)

Power-good (PGOOD) is an open-drain output of the built-in voltage supervisor that monitors DCDC1, DCDC2, DCDC3, DCDC4, and LDO1. The output is Hi-Z when all enabled rails are in regulation and driven low when one or more rails encounter a fault which brings the output voltage outside the specified tolerance range. In a typical application PGOOD drives the reset signal of the SOC.

The supervisor has two modes of operation, controlled by the STRICT bit. With the STRICT bit set to 0, all enabled rails of the five regulators are monitored for undervoltage only with relaxed thresholds and deglitch times. With the STRCT bit set to 1, all enabled rails of the five regulators are monitored for undervoltage and overvoltage with tight limits and short deglitch times. Table 7-1 summarizes these details.

Table 7-1 Supervisor Characteristics Controlled by the STRICT Bit
PARAMETER STRICT = 0b (TYP) STRICT =1b (TYP)
Undervoltage monitoring Threshold (output falling) 90% 96.5% (DCDC1 and DCDC2)
95.5% (DCDC3, DCDC4, and LDO1)
Deglitch (output falling) 1 ms 50 µs
Deglitch (output rising) 10 µs 10 µs
Overvoltage monitoring Threshold (output falling) N/A 103.5% (DCDC1 and DCDC2)
104.5% (DCDC3, DCDC4, and LDO1)
Deglitch (output falling) N/A 1 ms
Deglitch (output rising) N/A 50 µs
GUID-C66C7EF6-D8AC-4442-AAD1-881187758BA5-low.gif Figure 7-7 Definition of Undervoltage, Overvoltage Thresholds, Hysteresis, and Deglitch Times

The following rules apply to the PGOOD output:

  • The power-up default state for THE PGOOD is low. When all rails are disabled, the PGOOD output is driven low.
  • Only enabled rails are monitored. Disabled rails are ignored.
  • Power-good monitoring of a particular rail starts 5 ms after the rail is enabled and is continuously monitored thereafter. This allows the rail to power-up.
  • The PGOOD is delayed by PGDLY time after the sequencer is finished and the last rail is enabled.
  • If an enabled rail is continuously outside the monitoring threshold for longer than the deglitch time, then the PGOOD is pulled low, and all rails are shut-down following the power-down sequence. PGDLY does not apply.
  • Disabling a rail manually by resetting the DCx_EN or LDO1_EN bit has no effect on the PGOOD pin. If all rails are disabled, the PGOOD is driven low as the last rail is disabled.
  • If the power-down sequencer is triggered, PGOOD is driven low.
  • The PGOOD is driven low in the SUSPEND state, regardless of the number of rails that are enabled.

Figure 7-8 shows a typical power-up sequence and PGOOD timing.

GUID-D7ED905B-0203-4F12-96DC-6E99935C04CA-low.gif
A. Sequence shown for TPS65218D0 variant. For other TPS65218xx variants, refer to registers SEQ1-7 in Section 7.5.4 for factory-programmed sequence order and timing.
Figure 7-8 Typical Power-Up Sequence of the Main Output Rails