The TPS6521855 hosts a slave I²C interface (address 0x24) that supports data rates up to 400 kbps, auto-increment addressing. ⁽¹⁾

Figure 7-23 Subaddress in I²C Transmission

The I²C bus is a communications link between a controller and a series of slave terminals. The link is established using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is sourced from the controller in all cases where the serial data line is bi-directional for data communication between the controller and the slave terminals. Each device has an open drain output to transmit data on the serial data line. An external pullup resistor must be placed on the serial data line to pull the drain output high during data transmission.

Data transmission initiates with a start bit from the controller as shown in Figure 7-25. The start condition is recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon reception of a start bit, the device receives serial data on the SDA input and checks for valid address and control information. If the appropriate slave address is set for the device, the device issues an acknowledge pulse and prepares to receive register address and data. Data transmission is completed by either the reception of a stop condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An acknowledge issues after the reception of valid slave address, register-address, and data words. The I²C interfaces an auto-sequence through the register addresses, so that multiple data words can be sent for a given I²C transmission. Reference Figure 7-24 and Figure 7-25 for details.

Top: Master Writes Data to Slave

Bottom: Master Reads Data from Slave

Figure 7-24 I²C Data Protocol

Figure 7-25 I²C Protocol and Transmission Timing I²C Start Stop and Acknowledge Protocol

Figure 7-26 I²C Protocol and Transmission Timing I²C Data Transmission Timing