JAJSE75B December 2017 – September 2018 TPS65218D0
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
ENABLE1 is shown in Figure 5-45 and described in Table 5-17.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DC6_EN | DC5_EN | DC4_EN | DC3_EN | DC2_EN | DC1_EN | |
R-0h | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h |
|
5 | DC6_EN | R/W | 0b |
DCDC6 enable bit. DCDC6 can only be disabled if FSEAL = 0. See Section 5.6.2 for details. 0b = Disabled 1b = Enabled |
4 | DC5_EN | R/W | 0b |
DCDC5 enable bit. Note: At power-up/down this bit is automatically updated by the internal power sequencer. DCDC5 can only be disabled if FSEAL = 0. See Section 5.6.2 for details. 0b = Disabled 1b = Enabled |
3 | DC4_EN | R/W | 0b |
DCDC4 enable bit. Note: At power-up/down this bit is automatically updated by the internal power sequencer. 0b = Disabled 1b = Enabled |
2 | DC3_EN | R/W | 0b |
DCDC3 enable bit. Note: At power-up/down this bit is automatically updated by the internal power sequencer. 0b = Disabled 1b = Enabled |
1 | DC2_EN | R/W | 0b |
DCDC2 enable bit. Note: At power-up/down this bit is automatically updated by the internal power sequencer. 0b = Disabled 1b = Enabled |
0 | DC1_EN | R/W | 0b |
DCDC1 enable bit. Note: At power-up/down this bit is automatically updated by the internal power sequencer. 0b = Disabled 1b = Enabled |