JAJSOP6B May 2022 – June 2024 TPS65219
PRODUCTION DATA
PIN NAME | PIN NO. | TYPE | DESCRIPTION | CONNECTION if not used (output rails must be permanently disabled) |
---|---|---|---|---|
FB_B1 | 1 | I | Feedback Input for Buck1. Connect to Buck1 output filter. Nominal output voltage is configured in EEPROM. | Connect to GND |
LX_B1_1 | 2 | PWR | Switch Pin for Buck1. Connect one side of the Buck1-inductor to this pin. | Leave floating |
LX_B1_2 | 3 | PWR | 2nd Switch Pin for Buck1. Connect one side of the Buck1-inductor to this pin. Connect to LX_B1_1. | Leave floating |
PVIN_B1_1 | 4 | PWR | Power Input for BUCK1. Bypass this pin to ground with a 4.7 μF or greater ceramic capacitor. Voltage on PVIN_B1_1 pin must not exceed voltage on VSYS pin. | Connect to VSYS |
PVIN_B1_2 | 5 | PWR | 2nd Power Input for BUCK1. This pin shares the bypass capacitor from pin 4. Voltage on PVIN_B1_2 pin must not exceed voltage on VSYS pin. | Connect to VSYS |
PVIN_LDO1 | 6 | PWR | Power Input for LDO1. Voltage on PVIN_LDO1 pin must not exceed voltage on VSYS pin. | Connect to VSYS |
VLDO1 | 7 | PWR | Output Voltage of LDO1. Nominal output voltage is configured in EEPROM. Bypass this pin to ground with a 2.2 µF or greater ceramic capacitor. | Leave floating |
GPO1 | 8 | O | General Purpose Open-Drain Output. Configurable in the power-up and power-down-sequence to enable an external rail. | Leave floating |
SDA | 9 | I/O | Data Pin for the I2C Serial Port. The I2C logic levels depend on the external pull-up voltage. | Connect to VIO |
SCL | 10 | I | Clock Pin for the I2C Serial Port. The I2C logic levels depend on the external pull-up voltage. | Connect to VIO |
nINT | 11 | O | Interrupt Request Output. Open-drain driver is pulled low for fault conditions. Released if bit is cleared | Leave floating |
VSEL_SD/ VSEL_DDR | 12 | I | Multi-Function-Pin: Configured as VSEL_SD: SD-card-IO-voltage select. Connected to SoC. Trigger a voltage change between 1.8 V and register-based VOUT on LDO1 or LDO2. Polarity is configurable. Configured as VSEL_DDR: DDR-voltage selection. Hard-wired pull-up (1.35 V), pull-down (register based VOUT) or floating (1.2 V) |
n/a (connect to GND) |
VSYS | 13 |
PWR |
Input supply pin for reference system. Bypass this pin to ground with a 2.2 µF or greater ceramic capacitor (can be shared with PVIN-capacitors). | n/a |
VDD1P8 | 14 | PWR | Internal Reference Voltage: For Internal Use Only. Bypass this pin to ground with a 2.2 µF or greater ceramic capacitor. | n/a |
AGND | 15 | GND | Ground pin for Analog GND | n/a |
GPIO | 16 | I/O |
GPO-configuration: General Purpose Open-Drain Output. Configurable in the power-up and power-down-sequence to enable an external rail. GPIO-configuration: Synchronizing I/O. Used to synchronize two or more TPS65219. The pin is level-sensitive. |
Leave floating |
GPO2 | 17 | O | General Purpose Open-Drain Output. Configurable in the power-up and power-down-sequence to enable an external rail. | Leave floating |
nRSTOUT | 18 | O | Reset-output to SoC. Controlled by sequencer. High in ACTIVE and STBY state. | Leave floating |
VLDO2 | 19 | PWR | Output Voltage of LDO2. Nominal output voltage is configured in EEPROM. Bypass this pin to ground with a 2.2 µF or greater ceramic capacitor. | Leave floating |
PVIN_LDO2 | 20 | PWR | Power Input for LDO2. Bypass this pin to ground with a 2.2 μF or greater ceramic capacitor. Voltage on PVIN_LDO2 pin must not exceed voltage on VSYS pin. | Connect to VSYS |
VLDO3 | 21 | PWR | Output Voltage of LDO3. Nominal output voltage is configured in EEPROM. Bypass this pin to ground with a 2.2 µF or greater ceramic capacitor. | Leave floating |
PVIN_LDO34 | 22 | PWR | Power Input for LDO3 and LDO4. Bypass this pin to ground with a 4.7 μF or greater ceramic capacitor. Voltage on PVIN_LDO34 pin must not exceed voltage on VSYS pin. | Connect to VSYS |
VLDO4 | 23 | PWR | Output Voltage of LDO4. Nominal output voltage is configured in EEPROM.Bypass this pin to ground with a 2.2 µF or greater ceramic capacitor. | Leave floating |
FB_B3 | 24 | I | Feedback Input for Buck3. Connect to Buck3 output filter. Nominal output voltage is configured in EEPROM. | Connect to GND |
EN/PB/VSENSE | 25 | I | ON-request input. Configured as EN: Device enable pin, high level is ON-request, low-level is OFF-request. Configured as PB: Push-button monitor input. 600 ms low-level is an ON-request, 8 s low-level is an OFF-request. Configured as VSENSE: Power-fail comparator input. Set sense voltage using a resistor divider connected from the input to the pre-regulator to this pin to ground. Detects rising/falling voltage on pre-regulator and triggers ON- / OFF-request. The pin is edge-sensitive with a wait-time in PB-configuration and deglitch time for EN- and VSENSE-configuration. |
n/a (configure as EN and connect to VSYS) |
PVIN_B3 | 26 | PWR | Power Input for BUCK3. Bypass this pin to ground with a 4.7 μF or greater ceramic capacitor. Voltage on PVIN_B3 pin must not exceed voltage on VSYS pin. | Connect to VSYS |
LX_B3 | 27 | PWR | Switch Pin for Buck3. Connect one side of the Buck3-inductor to this pin. | Leave floating |
MODE/RESET | 28 | I | Multi-Function-Pin:
Configured as MODE: Connected to SoC or hard-wired pull-up/-down. Forces the Buck-converters into PWM or permits auto-entry in PFM-mode. Configured as RESET: Connected to SoC. Forces a WARM or COLD reset (configurable), WARM reset resetting output voltages to defaults, COLD reset sequencing down all enabled rails and power up again. Polarity is configurable. The pin is level-sensitive for MODE-configuration, edge-sensitive for RESET-configuration. |
n/a (tie high or low, dependent on configuration, see 'PWM/PFM and Reset (MODE/RESET)' |
LX_B2 | 29 | PWR | Switch Pin for Buck2. Connect one side of the Buck2-inductor to this pin. | Leave floating |
PVIN_B2 | 30 | PWR | Power Input for BUCK2. Bypass this pin to ground with a 4.7 μF or greater ceramic capacitor. Voltage on PVIN_B2 pin must not exceed voltage on VSYS pin. | Connect to VSYS |
MODE/STBY | 31 | I | Multi-Function-Pin: Configured as MODE: Connected to SoC or hard-wired pull-up/-down. Forces the Buck-converters into PWM or permits auto-entry in PFM-mode. Configured as STBY: Low-power-mode command, disables selected rails. Both functions, MODE and STBY, can be combined. The pin is level-sensitive. |
n/a (tie high or low, dependent on configuration, see 'PWM/PFM and Low Power Modes (MODE/STBY)' |
FB_B2 | 32 | I | Feedback Input for Buck2. Connect to Buck2 output filter. Nominal output voltage is configured in EEPROM. | Connect to GND |
PGND | PowerPad | GND | Power-Ground. The exposed pad must be connected to a continuous ground plane of the printed circuit board by multiple interconnect vias directly under the TPS65219 to maximize electrical and thermal conduction. | n/a |