JAJSOP6B May   2022  – June 2024 TPS65219

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  System Control Thresholds
    6. 6.6  BUCK1 Converter
    7. 6.7  BUCK2, BUCK3 Converter
    8. 6.8  General Purpose LDOs (LDO1, LDO2)
    9. 6.9  General Purpose LDOs (LDO3, LDO4)
    10. 6.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 6.11 Voltage and Temperature Monitors
    12. 6.12 I2C Interface
    13. 6.13 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequencing
      2. 7.3.2  Power-Down Sequencing
      3. 7.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 7.3.4  Reset to SoC (nRSTOUT)
      5. 7.3.5  Buck Converters (Buck1, Buck2, and Buck3)
      6. 7.3.6  Linear Regulators (LDO1 through LDO4)
      7. 7.3.7  Interrupt Pin (nINT)
      8. 7.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 7.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 7.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 7.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 7.3.12 I2C-Compatible Interface
        1. 7.3.12.1 Data Validity
        2. 7.3.12.2 Start and Stop Conditions
        3. 7.3.12.3 Transferring Data
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 OFF State
        2. 7.4.1.2 INITIALIZE State
        3. 7.4.1.3 ACTIVE State
        4. 7.4.1.4 STBY State
        5. 7.4.1.5 Fault Handling
    5. 7.5 Multi-PMIC Operation
    6. 7.6 User Registers
    7. 7.7 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application Example
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 8.2.3.2 LDO1, LDO2 Design Procedure
        3. 8.2.3.3 LDO3, LDO4 Design Procedure
        4. 8.2.3.4 VSYS, VDD1P8
        5. 8.2.3.5 Digital Signals Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Device Comparison

Table 4-1 lists a brief summary of the pre-configured orderable part numbers (OPNs) and the recommended application use case. This table also includes the collateral resources that are available to support new designs. The Applications note describes how the power and digital resources of the TPS65219 PMIC are used to meet the requirements of specific processors and MCUs. A full summary of the default non-volatile memory (NVM) register settings for each orderable can be found in the Technical Reference Manual (TRM).

The TPS6521905 is the user-programmable version that comes with all the power rails OFF by default and can be programmed to meet the power requirements of any processors or SoCs.

Table 4-1 Device Comparison Table for TI Processors and MCUs
Device Name Processor / MCU Application Use Case Collateral
Vin Memory VDD_CORE TRM Apps Note
TPS6521901 AM62x, AM62x SIP, AM64 5 V DDR4 0.75 V SLVUCH3
TPS6521902 AM62x, AM62x SIP, AM64 3.3 V or 5 V LPDDR4 0.75 V SLVUCL0
TPS6521903 (1) AM62x, AM62x SIP, AM64 3.3 V or 5 V DDR4 0.75 V SLVUCJ2
TPS6521904 (1) AM62x, AM62x SIP, AM64, AM243 3.3 V or 5 V DDR4 0.85 V SLVUCL1
TPS6521907 AM62x, AM62x SIP, AM64, AM243 5 V DDR4 0.85 V SLVUCL9
TPS6521908 AM62x, AM62x SIP, AM64, AM243 3.3 V or 5 V LPDDR4 0.85 V SLVUCM0
TPS6521905 User-Programmable Version ANY ANY ANY TPS65219 Non-Volatile Memory (NVM) Programming Guide

(1) The AM62B starter kit with PMIC comes with the TPS6521904 by default, supporting VDD_CORE=0.85V. This hardware can also be modified to support VDD_CORE=0.75V using the TPS6521903 PMIC.