JAJSRG7A September   2023  – June 2024 TPS6521905-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1, LDO2)
    9. 5.9  General Purpose LDOs (LDO3, LDO4)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
      6. 6.3.6  Linear Regulators (LDO1 through LDO4)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6521905-Q1 default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1, LDO2 Design Procedure
        3. 7.2.3.3 LDO3, LDO4 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Fault Handling

Detectable Faults

The TPS6521905-Q1 offers various fault-detections. Per default, all of them lead to a sequenced shut-down. Some of them are maskable and the reaction to masked faults is configurable.

The device provides the following fault-detections on the supply voltage (VSYS) and internal voltage supply (VDD1P8):

  • Undervoltage on VSYS, resulting in transition to OFF state or gating start-up
  • Overvoltage-protection on VSYS, resulting in transition to OFF state
  • Under- or Overvoltage on internal 1.8V-supply (VDD1P8), resulting in transition to OFF state or gating start-up.

None of these faults are maskable.

The TPS6521905-Q1 provides the following fault-detections on the buck- and LDO-outputs:

  • Undervoltage detection (UV)
  • Over Current detection (OC), triggering on positive as well as (for buck-converters) negative current-limit
  • Short-to-GND detection (SCG)
  • Temperature warning (WARM) and Thermal Shut Down (TSD / HOT)
  • Residual Voltage (RV) and Residual Voltage - Shutdown (RV_SD)
  • Timeout (TO)
SCG, OC, HOT, RV_SD and TO are not maskable. If any one of those occurs, the device powers down. Positive and negative current limit share the same mask-bit per regulator.

The reaction to UV, RV and WARM faults is configurable. If not masked, a fault triggers a sequenced shut-down. UV, RV and WARM can be masked individually per regulator in INT_MASK_BUCKS, INT_MASK_LDOS and INT_MASK_WARM registers. No state-transition occurs in case of a masked fault. Whether bits are set and if nINT is pulled low can be configured globally by MASK_EFFECT bits in MASK_CONFIG register. Positive and negative current limit share the same mask-bit per regulator.

  • 00b = no state change, no nINT reaction, no bit set
  • 01b = no state change, no nINT reaction, bit set
  • 10b = no state change, nINT reaction, bit set (same as 11b)
  • 11b = no state change, nINT reaction, bit set (same as 10b)

For any fault that corresponds to a shut-down condition, the fault-bit remains asserted until a W1C (write-one-clear) operation is performed via I2C (assuming the fault is not present any more). In case of a shut-down fault, no renewed on-request is required. The device automatically executes the power up sequence if the fault is no longer present as long as EN/VSENSE is still high and no PB-press is required for a restart.

For any fault that is not a shut-down condition (for example because the fault is masked), the bit is cleared when going to the INITIALIZE state.

Thermal Warning and Shutdown

There are two thermal thresholds: Thermal-warning (WARM) and Thermal Shutdown (TSD / HOT).

  • Thermal Warning, WARM-threshold:
  • if the temperature exceeds TWARM_Rising threshold, the SENSOR_x_WARM-bit is set and the PMIC sequences down (unless masked).
  • if the temperature fell below TWARM_Falling threshold, the device powers up again, without a new
 Push-button-ON_Request. In EN or VSENSE configuration, the ON-request must still be valid to transition to ACTIVE state.
  • if the temperature exceeds TWARM_Rising threshold, but SENSOR_x_WARM_MASK bit is /bits are set, the PMIC remains in ACTIVE state. Fault-reporting occurs as configured by MASK_EFFECT bits. The processor makes the decision to either sequence the power down or throttles back on the running applications to reduce the power consumption and hopefully avoiding a Thermal Shutdown situation.
  • Thermal Shutdown, HOT-threshold, applicable if WARM-threshold is masked:
  • if the temperature exceeds THOT_Rising threshold, the SENSOR_x_HOT-bit is set and the PMIC powers off all rails immediately. This power down is simultaneously and not sequenced.
  • in case ALL sensors are masked for WARM-detection (all SENSOR_x_WARM_MASK bits are set), the PMIC does power back up once the temperature drops below the THOT_Falling threshold, provided a valid ON-request is present.
  • in case any one of the sensors is unmasked for WARM-detection, the PMIC does power back up once the temperature drops below the TWARM_Falling threshold, without a new
 Push-button-ON_Request. In EN or VSENSE configuration, the ON-request must still be valid to transition to ACTIVE state.

Residual Voltage

Residual voltage checks are performed at various occasions: before starting the INITIALIZE- to ACTIVE-transition and any time before a rail is enabled, regardless if during the sequence, by I2C-command or during the STBY- to ACTIVE-transition. RV-checks are also performed during the sequences, to detect if a rail that is supposed to be disabled is pulled up by another rail. The treatment of RV-faults depends on the situation when the fault occurs:

  • INITIALIZE to ACTIVE:
    • if residual voltage is detected for more than 4 ms to 5 ms prior to the execution of the sequence, the respective INT_RV_IS_SET bit in INT_SOURCE register and LDOx_RV respectively BUCKx_RV bit in INT_RV register is set and remains set, even if the discharge is successful at a later time and the ON-request is executed.
    • if the residual voltage is detected during the sequence, this constitutes a shutdown-fault: the device initiates the power-down-sequence at the end of the slot-duration. The device sets the respective INT_TIMEOUT_RV_SD_IS_SET bit in INT_SOURCE register, LDOx_RV_SD respectively BUCKx_RV_SD bit and bit TIMEOUT in INT_TIMEOUT_RV_SD register.
  • ACTIVE to STBY:
    • if active discharge is enabled and residual voltage is detected after eight times the power-down slot-duration, this constitutes a shutdown-fault: the device sequences down at the end of the slot. The device sets INT_TIMEOUT_RV_SD_IS_SET bit in INT_SOURCE register, the LDOx_RV_SD respectively BUCKx_RV_SD bit and the bit TIMEOUT in INT_TIMEOUT_RV_SD register.
    • if the residual voltage is detected during the sequence, this constitutes a shutdown-fault: the device sequences down at the end of the slot-duration and sets bit INT_TIMEOUT_RV_SD_IS_SET in INT_SOURCE register and LDOx_RV_SD respectively BUCKx_RV_SD bit in INT_TIMEOUT_RV_SD register.
  • STBY to ACTIVE:
    • if residual voltage is detected prior to the execution of the sequence for more than 4 ms to 5 ms, the device sets INT_RV_IS_SET bit in INT_SOURCE register and LDOx_RV respectively BUCKx_RV bit in INT_RV register. The bit remains set, even if the discharge is successful before timeout expires and the STBY-to-ACTIVE-sequence is executed.
    • if residual voltage is detected for more than 80 ms prior to the execution of the sequence, this constitutes a shutdown-fault: the device sequences down and sets the bit INT_TIMEOUT_RV_SD_IS_SET in INT_SOURCE register and LDOx_RV_SD respectively BUCKx_RV_SD bit in INT_TIMEOUT_RV_SD register. In addition, the device sets the bit TIMEOUT in INT_TIMEOUT_RV_SD register.
    • if the residual voltage is detected during the sequence, this constitutes a shutdown-fault: the device sequences down at the end of the slot-duration and sets the INT_TIMEOUT_RV_SD_IS_SET bit in INT_SOURCE register and LDOx_RV_SD respectively BUCKx_RV_SD bit in INT_TIMEOUT_RV_SD register. The TIMEOUT bit is not set in this case.
  • ACTIVE to INITIALIZE or STBY to INITIALIZE
    • if the residual voltage is detected at the end of the power-down slot-duration of the respective rail, this gates the disabling of the subsequent rail for up to eight times the slot-duration, but then the power-sequence continues regardless of the residual voltage. No bit is set in this case.
  • MASKING of RV-bits
    • the reaction of the nINT-pin reaction in case of residual voltage detection is maskable for LDOx_RV respectively BUCKx_RV bits by MASK_INT_FOR_RV bit in MASK_CONFIG register.
    • neither the bit nor the shutdown-fault-reaction in case of residual voltage detection is maskable for LDOx_RV_SD respectively BUCKx_RV_SD bits.
  • Timeout
    • Timeout occurs if residual voltage cannot be discharged in time. The bit TIMEOUT in INT_TIMEOUT_RV_SD register is set. See details above.
Note: In case active discharge on a rail is disabled, the unsuccessful discharge of that rail within the slot duration does not gate the disable of the subsequent rail.

During power-down, the device sets neither RV-bits nor RV_SD-bits for rails with disabled discharge.

CAUTION: For every detected Shut-Down fault, irrespective if prior to the sequence due to unsuccessful discharge, during the power-up-sequence or in ACTIVE or STBY state, the retry counter (RETRY_COUNT in POWER_UP_STATUS_REG register) is incremented. The device attempts two retries to power-up. If both fail, a power-cycle on VSYS is required to reset the retry counter. Any successful power-up also resets the retry counter.

If faults are masked and do not cause a shut-down, the retry counter does not increment.

To disable the retry-counter, set bit MASK_RETRY_COUNT in INT_MASK_UV register. When set, the device attempts to retry infinitely.

Below table gives an overview of the fault-behavior in ACTIVE and STBY states if unmasked and whether a fault is maskable.
CAUTION: Masking of faults can pose a risk to the device or the system, including but not limited to starting into a pre-biased output.

It is strongly discouraged to mask OC- and UV-detection on the same rail.

Table 6-6 Fault Handling
Block Fault ACTIVE or STBY state (if fault NOT masked) ACTIVE or STBY state (if fault IS masked)
BUCK & LDO Residual voltage - shutdown-Fault - RV_SD *) Fault triggers a sequenced shut-down to INITIALIZE state Not maskable
BUCK & LDO Residual voltage - RV Fault does not trigger state-change Fault does not trigger state-change
BUCK & LDO Timeout - TO *) Fault triggers a sequenced shut-down to INITIALIZE state Fault does not trigger state-change
BUCK & LDO Undervoltage - UV Fault triggers a sequenced shut-down to INITIALIZE state Fault does not trigger state-change
BUCK & LDO Overcurrent - OC Fault triggers a sequenced shut-down to INITIALIZE state Not maskable
BUCK & LDO Short-to-GND - SCG Fault triggers a sequenced shut-down to INITIALIZE state Not maskable
BUCK & LDO Temperature warning - WARM Fault triggers a sequenced shut-down to INITIALIZE state Yes
BUCK & LDO Temperature shut-down - HOT Fault triggers an immediate shut-down to INITIALIZE state (not sequenced) Not maskable
VSYS Undervoltage - UV Fault triggers an immediate shut-down to OFF state (not sequenced) Not maskable
VSYS Overvoltage - OV Fault triggers an immediate shut-down to OFF state (not sequenced) Not maskable
VDD1P8 Undervoltage or Overvoltage - UV or OV Fault triggers an immediate shut-down to OFF state (not sequenced) Not maskable

*) RV_SD and TIMEOUT faults can only occur during a sequence