Detectable Faults

The TPS6521905-Q1 offers various fault-detections. Per default, all of them lead to a sequenced shut-down. Some of them are maskable and the reaction to masked faults is configurable.

The device provides the following fault-detections on the supply voltage (VSYS) and internal voltage supply (VDD1P8):

• Undervoltage on VSYS, resulting in transition to OFF state or gating start-up
• Overvoltage-protection on VSYS, resulting in transition to OFF state
• Under- or Overvoltage on internal 1.8V-supply (VDD1P8), resulting in transition to OFF state or gating start-up.

None of these faults are maskable.

The TPS6521905-Q1 provides the following fault-detections on the buck- and LDO-outputs:

• Undervoltage detection (UV)
• Over Current detection (OC), triggering on positive as well as (for buck-converters) negative current-limit
• Short-to-GND detection (SCG)
• Temperature warning (WARM) and Thermal Shut Down (TSD / HOT)
• Residual Voltage (RV) and Residual Voltage - Shutdown (RV_SD)
• Timeout (TO)

The reaction to UV, RV and WARM faults is configurable. If not masked, a fault triggers a sequenced shut-down. UV, RV and WARM can be masked individually per regulator in INT_MASK_BUCKS, INT_MASK_LDOS and INT_MASK_WARM registers. No state-transition occurs in case of a masked fault. Whether bits are set and if nINT is pulled low can be configured globally by MASK_EFFECT bits in MASK_CONFIG register. Positive and negative current limit share the same mask-bit per regulator.

• 00b = no state change, no nINT reaction, no bit set
• 01b = no state change, no nINT reaction, bit set
• 10b = no state change, nINT reaction, bit set (same as 11b)
• 11b = no state change, nINT reaction, bit set (same as 10b)

For any fault that corresponds to a shut-down condition, the fault-bit remains asserted until a W1C (write-one-clear) operation is performed via I2C (assuming the fault is not present any more). In case of a shut-down fault, no renewed on-request is required. The device automatically executes the power up sequence if the fault is no longer present as long as EN/VSENSE is still high and no PB-press is required for a restart.

For any fault that is not a shut-down condition (for example because the fault is masked), the bit is cleared when going to the INITIALIZE state.

Thermal Warning and Shutdown

There are two thermal thresholds: Thermal-warning (WARM) and Thermal Shutdown (TSD / HOT).

• Thermal Warning, WARM-threshold:
• if the temperature exceeds T_{WARM_Rising} threshold, the SENSOR_x_WARM-bit is set and the PMIC sequences down (unless masked).
• if the temperature fell below T_{WARM_Falling} threshold, the device powers up again, without a new
 Push-button-ON_Request. In EN or VSENSE configuration, the ON-request must still be valid to transition to ACTIVE state.
• if the temperature exceeds T_{WARM_Rising} threshold, but SENSOR_x_WARM_MASK bit is /bits are set, the PMIC remains in ACTIVE state. Fault-reporting occurs as configured by MASK_EFFECT bits. The processor makes the decision to either sequence the power down or throttles back on the running applications to reduce the power consumption and hopefully avoiding a Thermal Shutdown situation.
• Thermal Shutdown, HOT-threshold, applicable if WARM-threshold is masked:
• if the temperature exceeds T_{HOT_Rising} threshold, the SENSOR_x_HOT-bit is set and the PMIC powers off all rails immediately. This power down is simultaneously and not sequenced.
• in case ALL sensors are masked for WARM-detection (all SENSOR_x_WARM_MASK bits are set), the PMIC does power back up once the temperature drops below the T_{HOT_Falling} threshold, provided a valid ON-request is present.
• in case any one of the sensors is unmasked for WARM-detection, the PMIC does power back up once the temperature drops below the T_{WARM_Falling} threshold, without a new
 Push-button-ON_Request. In EN or VSENSE configuration, the ON-request must still be valid to transition to ACTIVE state.

Residual Voltage

Residual voltage checks are performed at various occasions: before starting the INITIALIZE- to ACTIVE-transition and any time before a rail is enabled, regardless if during the sequence, by I2C-command or during the STBY- to ACTIVE-transition. RV-checks are also performed during the sequences, to detect if a rail that is supposed to be disabled is pulled up by another rail. The treatment of RV-faults depends on the situation when the fault occurs:

• INITIALIZE to ACTIVE:
  • if residual voltage is detected for more than 4 ms to 5 ms prior to the execution of the sequence, the respective INT_RV_IS_SET bit in INT_SOURCE register and LDOx_RV respectively BUCKx_RV bit in INT_RV register is set and remains set, even if the discharge is successful at a later time and the ON-request is executed.
  • if the residual voltage is detected during the sequence, this constitutes a shutdown-fault: the device initiates the power-down-sequence at the end of the slot-duration. The device sets the respective INT_TIMEOUT_RV_SD_IS_SET bit in INT_SOURCE register, LDOx_RV_SD respectively BUCKx_RV_SD bit and bit TIMEOUT in INT_TIMEOUT_RV_SD register.
• ACTIVE to STBY:
  • if active discharge is enabled and residual voltage is detected after eight times the power-down slot-duration, this constitutes a shutdown-fault: the device sequences down at the end of the slot. The device sets INT_TIMEOUT_RV_SD_IS_SET bit in INT_SOURCE register, the LDOx_RV_SD respectively BUCKx_RV_SD bit and the bit TIMEOUT in INT_TIMEOUT_RV_SD register.
  • if the residual voltage is detected during the sequence, this constitutes a shutdown-fault: the device sequences down at the end of the slot-duration and sets bit INT_TIMEOUT_RV_SD_IS_SET in INT_SOURCE register and LDOx_RV_SD respectively BUCKx_RV_SD bit in INT_TIMEOUT_RV_SD register.
• STBY to ACTIVE:
  • if residual voltage is detected prior to the execution of the sequence for more than 4 ms to 5 ms, the device sets INT_RV_IS_SET bit in INT_SOURCE register and LDOx_RV respectively BUCKx_RV bit in INT_RV register. The bit remains set, even if the discharge is successful before timeout expires and the STBY-to-ACTIVE-sequence is executed.
  • if residual voltage is detected for more than 80 ms prior to the execution of the sequence, this constitutes a shutdown-fault: the device sequences down and sets the bit INT_TIMEOUT_RV_SD_IS_SET in INT_SOURCE register and LDOx_RV_SD respectively BUCKx_RV_SD bit in INT_TIMEOUT_RV_SD register. In addition, the device sets the bit TIMEOUT in INT_TIMEOUT_RV_SD register.
  • if the residual voltage is detected during the sequence, this constitutes a shutdown-fault: the device sequences down at the end of the slot-duration and sets the INT_TIMEOUT_RV_SD_IS_SET bit in INT_SOURCE register and LDOx_RV_SD respectively BUCKx_RV_SD bit in INT_TIMEOUT_RV_SD register. The TIMEOUT bit is not set in this case.
• ACTIVE to INITIALIZE or STBY to INITIALIZE
  • if the residual voltage is detected at the end of the power-down slot-duration of the respective rail, this gates the disabling of the subsequent rail for up to eight times the slot-duration, but then the power-sequence continues regardless of the residual voltage. No bit is set in this case.
• MASKING of RV-bits
  • the reaction of the nINT-pin reaction in case of residual voltage detection is maskable for LDOx_RV respectively BUCKx_RV bits by MASK_INT_FOR_RV bit in MASK_CONFIG register.
  • neither the bit nor the shutdown-fault-reaction in case of residual voltage detection is maskable for LDOx_RV_SD respectively BUCKx_RV_SD bits.
• Timeout
  • Timeout occurs if residual voltage cannot be discharged in time. The bit TIMEOUT in INT_TIMEOUT_RV_SD register is set. See details above.

*) RV_SD and TIMEOUT faults can only occur during a sequence