JAJSRG7A September   2023  – June 2024 TPS6521905-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1, LDO2)
    9. 5.9  General Purpose LDOs (LDO3, LDO4)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
      6. 6.3.6  Linear Regulators (LDO1 through LDO4)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6521905-Q1 default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1, LDO2 Design Procedure
        3. 7.2.3.3 LDO3, LDO4 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Multi-PMIC Operation

The GPIO (pin#16) is an input/output digital pin, however, the input-functionality is only used in multi-PMIC configuration. This pin behaves as GPO (general purpose output) when configured for single PMIC and behaves as GPIO (general purpose input-output) when configured for multi-device. This configuration can be made on register field MULTI_DEVICE_ENABLE (address 0x1F). When configured for "multi-device", GPIO allows to synchronize the power-up and power-down sequence of multiple TPS6521905-Q1 devices for applications requiring additional rails. The GPIO pin is used to indicate the status of each PMIC so they are always in the same state and same sequence slot. At the beginning of each sequence slot, all the TPS6521905-Q1 PMICs drive GPIO pin low. After the sequence slot duration finishes, and all rails for that slot have reached the UV threshold, device releases the GPIO pin. Once both devices release the GPIO high, they advance to the next sequence slot together. Since both PMICs are always in the same power-up or power-down slot, multiple rails from each PMIC can be assigned to the same sequence slot. Figure 6-11 shows an example PDN of two TPS6521905-Q1 devices sharing the same input supply (VSYS), EN pin and GPIO for multi-PMIC operation.

Requirements when synchronizing multiple TPS6521905-Q1 PMICs

  • The GPIO from each PMIC must be tied together, sharing the same pull-up resistor. The pull-up resistance needs to be chosen to meet the maximum allowable rise-time tRISE_GPIO in combination with the capacitance on the GPIO-line to allow for synchronization.
  • The EN/PB/VSENSE pin must be tied together sharing the same external ON request. This pin must have the same configuration (same pin config, deglitch, FSD).
  • All the TPS6521905-Q1 PMICs must share the same VSYS supply.
  • Each of the TPS6521905-Q1 PMICs must have a different I2C address if they are connected to the same I2C bus. The I2C address for the second PMIC can be changed on register field I2C_ADDRESS. Once the address is changed, the new value must be stored permanently into the NVM. Refer to NVM Programming for programming instructions.

Figure 6-11 Multi-PMIC Configuration Example
Note:
  • The synchronization-times between the PMICs add to the slot-duration-timeout described in the Power-up and Power-Down sections: If power-up fails, the timeout tTIMEOUT_UV_SLOT occurs 3ms to 4ms later in multi-PMIC-configurations. If power-down fails due to discharge failing, the timeout occurs 20 ms to 26 ms later in multi-PMIC configurations.
  • GPIO_EN and GPIO_STBY_EN bits are ignored in multi-PMIC configuration.

Figure 6-12 shows the synchronization between two PMICs in Initialize state, before the power-up sequence is executed. While in INITIALIZE state, before the ON request is received, devices hold GPIO low. GPIO is only released when the ON request is received. The external signal driving the ON request must be connected to EN/PB/VSENSE pin of both devices. The PMICs proceed to execute the power-up sequence once both devices are in INITIALIZE state and both devices have received the ON request. This technique ensures both devices start the power-up sequence at the same time, even if they have different internal boot-up times.

TPS6521905-Q1 Synchronization before Power-up Figure 6-12 Synchronization before Power-up

Figure 6-13 shows the synchronization between two PMICs during the power-up sequence. An open-drain GPIO is connected between both PMICs, and used as an indicator that the sequence slot has finished for the device. At the beginning of each sequence slot, both PMICs pull down this GPIO. After the device slot timer has expired, and all rails for that slot have reach UV threshold, the GPIO is released high. The combined GPIO goes high when both PMICs have released the GPIO. Once both devices release the GPIO high, both PMICs advance to the next sequence slot. Both PMICs are always in the same sequence slot at the same time.

TPS6521905-Q1 Synchronization during
                    power-up sequence Figure 6-13 Synchronization during power-up sequence

Figure 6-14 shows the synchronization between two PMICs when transitioning from Active to Standby. In active or standby, GPIO default state is high. When a device wants to change states, it sets the GPIO low for a specific low duration. The low duration determines the type of request. For STANDBY/ACTIVE request, GPIO is set low approximately 38-52us and for OFF request approximately 180-243us. Times are chosen such that devices always see the same state transition, accounting for clock variation and requests happening right after each other. While GPIO is low, devices are counting the time it is low. On GPIO rising edge, devices start the state transition based on low duration. If GPIO stays low longer than the timeout duration, it indicates a GPIO fault and devices transition to INITIALIZE state.

TPS6521905-Q1 Synchronization before transitioning to Standby/OFF request/COLD
                    RESET Figure 6-14 Synchronization before transitioning to Standby/OFF request/COLD RESET

Figure 6-15 shows the synchronization between two PMICs during power-down sequence. Power-down sequence works similarly. If active discharge is enabled for a rail, the sequence slot is extended until rail is discharged below SCG threshold, unless the slot timeout occurs or register field BYPASS_RAILS_DISCHA RGED_CHECK is set. If discharge is disabled for all rails in current slot, the actual slot time is only based on selected slot duration. Once the slot duration expires and rails with active discharge are discharged, devices release the GPIO high. Once all devices release GPIO high, they advance to the next power-down step.

TPS6521905-Q1 Synchronization during
                    power-down sequence Figure 6-15 Synchronization during power-down sequence

Figure 6-16 shows the timeout synchronization between two PMICs. In case of a fault on an output rail, GPIO is not released. After a timeout, device goes to “timeout synchronization” state, and wait for 3ms before setting GPIO high. Once the combined GPIO goes high, both devices start the power-down sequence. For example: If BUCK1 from PMIC A is shorted to GND, after the slot duration expires, the regulator does not have hit UV and GPIO is not released. If Slot#1 duration is 10ms and PMIC A is 10% fast, it only takes 9ms to timeout. After timeout, device goes to timeout-sync state, at which point GPIO is set high after 3ms. PMIC B rails ramp up properly, but a high state on GPIO from PMIC A is initially not detected due to the fault on BUCK1. PMIC B also goes to timeout-sync state and sets GPIO high after 3ms. After the timeout sync of PMIC B, the combined GPIO is high and both PMICs start power-down together.

TPS6521905-Q1 Timeout Synchronization Figure 6-16 Timeout Synchronization