The TPS6521905-Q1 offers a total of four linear regulators, where LDO1 and LDO2 share their properties and LDO3 and LDO4 share theirs.

LDO1 and LDO2: 400 mA, 0.6 V .. 3.4 V

Both, LDO1 and LDO2 are general-purpose LDOs intended to provide power to analog circuitry on the SOC or peripherals. The LDOs have an input voltage range from 1.5V to 5.5V, and can be connected either directly to the system power or the output of a Buck converter. The output voltage is programmable in the range of 0.6V to 3.4V in 50mV-steps. Both LDOs support up to 400 mA. The LDOs can be configured in by-pass-mode, acting as load-switches. If configured in bypass-mode, the desired output voltage still needs to be specified in LDOx_VOUT register. The LDOs also support output-voltage changes while enabled, supporting functions like SD-card-IO-supply, changing from 3.3V to 1.8V after initialization, either in LDO-mode at a supply-voltage above 3.3V or with a 3.3V supply changing between bypass-mode and LDO-mode. The LDOs also support Load-switch mode (LSW_mode): in this case, output voltages of 1.5V up to 5.5V are supported. The desired voltage does not need to be configured in the LDOx_VOUT register.

• In case of SD-card-supply, one of the LDOs can be controlled by the VSEL_SD/VSEL_DDR, configured as VSEL_SD. Which LDO is controlled is selected by VSEL_RAIL bit in MFP_1_CONFIG register. The polarity of the pin can be configured via VSEL_SD_POLARITY bit in MFP_1_CONFIG register.

  Alternatively, an I2C communication to VSEL_SD_I2C_CTRL in MFP_1_CONFIG register controls the change of the output voltage. Therefore, even if VSEL_SD/VSEL_DDR pin is configured as VSEL_DDR, the VSEL_RAIL bit still needs to be configured to define which LDO is affected by the I2C-command.

• The LDOs can be configured as linear regulators or operate in bypass-mode or be configured as a load-switch (LSW-mode). The mode is configured by LDOx_LSW_CONFIG and LSW_BYP_CONFIG bits in LDOx_VOUT register.

Output Capacitance Requirements

The LDO regulators require sufficient output-capacitance for stability. The required minimum and supported maximum capacitance depends on the configuration:

• in LDO-mode, a minimum capacitance of 1.6 uF is required and a maximum total load capacitance (output filter and point-of-load combined) of 20 uF is supported
• in LSW- or bypass-mode, a minimum capacitance of 1.6 uF is required and a maximum total capacitance (output filter and point-of-load combined) of 50 uF is supported

LDO3 and LDO4: 300 mA, 1.2 V .. 3.3 V

Both, LDO3 and LDO4 are general-purpose LDOs intended to provide power to analog circuitry on the SoC or peripherals. The LDOs have an input voltage range from 2.2 V to 5.5 V, and can be connected either directly to the system power or the output of a Buck converter. Note, these LDOs need a headroom between VSYS and the LDO-output voltage of minimum 150 mV. The output voltage is programmable in the range of 1.2 V to 3.3 V in 50 mV-steps. Both LDOs support up to 300 mA. The LDOs can be configured to act as load-switches. In this case, output voltages of 2.2 V up to 5.5 V are supported. The desired voltage does not need to be configured in the LDOx_VOUT register.

These LDOs support a fast-ramp-mode with limited output capacitance and a slow-ramp-mode, allowing for larger total load capacitance.

Output Capacitance Requirements

The LDO regulators require sufficient output-capacitance for stability. The required minimum and supported maximum capacitance depends on the configuration:

• for slow-ramp LDO-mode or LSW-mode, a minimum capacitance of 1.6 uF is required and a maximum total capacitance (output filter and point-of-load combined) of 30 uF is supported
• for fast-ramp LDO-mode or LSW-mode, a minimum capacitance of 1.6 uF is required and a maximum total capacitance (output filter and point-of-load combined) of 15 uF is supported

LDO1, LDO2, LDO3 and LDO4

• The ON/OFF state of the LDOs in ACTIVE state is controlled by the corresponding LDOx_EN bit in the ENABLE_CTRL register.
• The ON/OFF state of the LDOs in STBY state is controlled by the corresponding LDOx_STBY_EN bit in the STBY_1_CONFIG register.
• In INITIALIZE state, the LDOs are off, regardless of bit-settings.

• Each of the LDOs can be configured as linear regulators or be configured as a load-switch (LSW-mode). LDO1 and LDO2 can also operate in bypass-mode. The mode is configured by LDOx_LSW_CONFIG and LSW_BYP_CONFIG bits in LDOx_VOUT register individually per regulator.
  CAUTION: A mode change between LDO(/bypass) and LSW-mode must only be performed, when the regulator is disabled!

  (A change between LDO and bypass-mode (supported by LDO1 and LDO2 only) is supported during operation.)

• The LDOs have an active discharge function. Whenever LDOx is disabled, the output is discharged to ground. The discharge function can be disabled individually per rail in the DISCHARGE_CONFIG register.
• Prior to a sequence into ACTIVE state (from INITIALIZE or STBY state), the device discharges the disabled rails regardless of the discharge-configuration to avoid starting into a pre-biased output.
• If a rail is enabled by an I2C-command, active discharge is not enforced, but the rail is only enabled if the output voltage is below the SCG-threshold.
• This register is not EEPROM-backed and is reset if the device enters OFF-state.
• When in INITIALIZE state (during RESET or an I2C-OFF-request), the discharge configuration is not reset. Note: the power-down-sequence can be violated if the discharge function is disabled

LDO Fault Handling

• The TPS6521905-Q1 detects under-voltages on the LDO-outputs. The reaction to the detection of an under-voltage is dependent on the configuration of the LDOx_UV_MASK bit in INT_MASK_LDOS register and the MASK_EFFECT in INT_MASK_BUCKS register. If not masked, the device sets bit INT_LDO_1_2_IS_SET respectively INT_LDO_3_4_IS_SET bit in INT_SOURCE register and bit LDOx_UV in INT_LDO_1_2 register respectively INT_LDO_3_4 register.

  During a voltage transition (at power-up or triggered by toggling VSEL_SD-pin or an I2C-command), the device blanks the undervoltage detection by default and activates the undervoltage detection when the voltage transition completed.

  If the device detects an undervoltage during the sequence into ACTIVE state (from INITIALIZE or STBY) and UV is not masked, the power-down-sequence starts at the end of the current slot.

  If the device detects an undervoltage in ACTIVE-state or STBY-state and UV is not masked, the power-down sequence starts immediately. OC-detection is not maskable.

  CAUTION: If a LDO is configured in bypass-mode or LSW-mode, UV-detection is not supported.
• The TPS6521905-Q1 provides current-limit on the LDO-outputs. If the PMIC detects over-current for t_{DEGLITCH_OC_short}, respectively for t_{DEGLITCH_OC_long} (configurable individually per rail with EN_LONG_DEGL_FOR_OC_LDOx in OC_DEGL_CONFIG register; applicable for rising-edge only), the device sets INT_LDO_1_2_IS_SET respectively INT_LDO_3_4_IS_SET bit in INT_SOURCE register and bit LDOx_OC in INT_LDO_1_2 respectively INT_LDO_3_4 register. The effected rail is disabled immediately.

  During a voltage transition (at power-up or triggered by toggling VSEL_SD-pin or an I2C-command), the overcurrent detection is blanked and gets activated when the voltage transition completed.

  If the over-current occurs during the sequence into ACTIVE state (from INITIALIZE or STBY), the device disables the affected rail immediately and starts the power-down-sequence at the end of the current slot.

  If the over-current occurs in ACTIVE-state or STBY-state, the device disables the affected rail immediately and starts the power-down sequence.

  OC-detection is not maskable, but the deglitch-time is configurable. It is strongly recommended to use t_{DEGLITCH_OC_short}. Extended over-current can lead to increased aging or overshoot upon recovery.
  

• The TPS6521905-Q1 detects short-to-ground (SCG) faults on the LDO-outputs. The reaction to the detection of an SCG event is to set INT_LDO_1_2_IS_SET respectively INT_LDO_3_4_IS_SET bit in INT_SOURCE register and bit LDOx_SCG in INT_LDO_1_2 register respectively INT_LDO_3_4 register. The affected rail is disabled immediately. The device sequences down all outputs and transitions into INTIALIZE state.

  SCG-detection is not maskable.

  If a rail gets enabled, the device blanks SCG detection initially to allow the rail to ramp above the SCG-threshold.
  

• The TPS6521905-Q1 detects residual voltage (RV) faults on the LDO-outputs. The reaction to the detection of an RV event is to set INT_RV_IS_SET bit in INT_SOURCE register and bit LDOx_RV in INT_RV register. The RV-detection is not maskable, but the nINT-reaction can be configured globally for all rails by MASK_INT_FOR_RV in INT_MASK_WARM register. The device sets the LDOx_RV-flag regardless of masking, INT_RV_IS_SET bit is only set if nINT is asserted. The fault-reaction time and potential state-transition depends on the situation when the faults are detected:
  • If the device detects residual voltage during an ON-request in the INITIALIZE state, the PMIC gates power-up and the device remains in INITIALIZE state. If the RV-condition is detected for more than 4 ms to 5 ms, the device sets the LDOx_RV-bit but remains in INITIALIZE state as long as the RV-condition exists. If the RV-condition is not present any more, the device transitions to ACTIVE state, provided the ON-request is still valid.
  • If the device detects residual voltage during power-up, ACTIVE_TO_STANDBY, or STANDBY_TO_ACTIVE sequences, the sequence is aborted and the device powers down.
  • If the device detects residual voltage for more than 80 ms on any rail that was disabled during STBY state during a request to leave STBY state, the device transitions into INITIALIZE state. The device sets the LDOx_RV-bit if the condition persists for 4 ms to 5 ms, but less than 80 ms.
  • If the device detects residual voltage during power-up, ACTIVE_TO_STANDBY, or STANDBY_TO_ACTIVE sequences, the sequence is aborted and the device powers down.
  • If the device detects residual voltage during an EN-command of the rail by I2C, the LDOx_RV-bit is set immediately, but no state transition occurs.
• The LDOs have a local over-temperature sensor. The reaction to a temperature warning is dependent on the configuration of the respective SENSOR_x_WARM_MASK bit in and the MASK_EFFECT bit in INT_MASK_BUCKS register. If the temperature at the sensor exceeds T_{WARM_Rising} and is not masked, the device sets INT_SYSTEM_IS_SET bit in INT_SOURCE register and SENSOR_x_WARM bit in INT_SYSTEM register. In case the sensor detects a temperature exceeding T_{HOT_Rising} , the converters power dissipation and junction temperature exceeds safe operating value. The device powers down all active outputs immediately and sets INT_SYSTEM_IS_SET bit in INT_SOURCE register and SENSOR_x_HOT bit in INT_SYSTEM register. The TPS6521905-Q1 automatically recovers once the temperature drops below the T_{WARM_FAlling} threshold value (or below the T_{HOT_FAlling} threshold value in case T_WARM is masked). The _HOT bit remains set and needs to be cleared by writing '1'. The HOT-detection is not maskable.