JAJSRG7A September   2023  – June 2024 TPS6521905-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1, LDO2)
    9. 5.9  General Purpose LDOs (LDO3, LDO4)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
      6. 6.3.6  Linear Regulators (LDO1 through LDO4)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6521905-Q1 default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1, LDO2 Design Procedure
        3. 7.2.3.3 LDO3, LDO4 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)

over operating free-air temperature range (unless otherwise noted)
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics
9.1.1 VOL Low-level Output Voltage (open-drain) VIO = 3.6V, IOL = 2mA, GPO1, GPO2, GPIO, nRSTOUT, nINT 0.40 V
9.1.2 VIL Low-level Input Voltage EN/PB, MODE/STBY, MODE/RESET and VSEL_SD/VSEL_DDR, GPIO 0.4 V
9.1.3 VIH High-level Input Voltage EN/PB, MODE/STBY, MODE/RESET and VSEL_SD/VSEL_DDR, GPIO 1.26 V
9.1.4 VVSENSE VSENSE Comparator Threshold (EN/PB/VSENSE) 1.08 1.20 1.32 V
9.1.5 VVSENSE_HYS VSENSE Comparator Hysteresis (EN/PB/VSENSE) 8 30 55 mV
9.1.6 ILKG Input leakage current (GPIO, EN/PB/VSENSE, MODE/STBY, MODE/RESET, VSEL_SD/VSEL/DDR) VIN = 3.3 V 1.0 μA
9.1.7 CIN Internal input pin capacitance (GPIO, EN/PB/VSENSE, MODE/STBY, MODE/RESET, VSEL_SD/VSEL/DDR) 10 pF
9.1.8 IPD pull-down current, available 100us after VSYS is applied on pins GPO1, GPO2, GPIO, MODE/STBY, MODE/RESET, VSEL_SD/VSEL_DDR, nINT, nRSTOUT 18 25 35 nA
9.1.9 ILKG_VSYS_ONLY Pin leakage when VSYS is present, but digital supply VDD1P8 is not SDA only 1 μA
9.1.10 VPIN_VSYS_ONLY Pin voltage when VSYS is present, but digital supply VDD1P8 is not GPO1, GPO2, GPIO, nRSTOUT, nINT, IOL=2mA 0.4 V
Timing Requirements
9.2.1a tFALL Output buffer fall time (90% to 10%) GPO1, GPO2, GPIO, nRSTOUT, nINT, COUT = 10pF 50 ns
9.2.1b tRISE GPIO Output buffer rise time (10% to 90%) GPIO, applicable in Multi-PMIC-configuration 5 μs
9.2.1.1 tDLY_FALL Output buffer falling time delay
(input crossing 50% to output crossing 50%)		 COUT = 10pF 50 ns
9.2.2.1 tDLY_RISE Open Drain Output buffer rising time delay
(digital input to output crossing 50%)		 COUT = 10pF, RPU=1k (external pull up), VIO = 1.8V 300 ns
9.2.2.3 FLT_HIGHDuration Time the digital has allotted for the test to see if the pin can be pulled high internally COUT = 10pF 15 μs
9.2.2.4 FLT_LOWDuration Time the digital has allotted for the test to see if the pin can be pulled low internally COUT = 10pF 15 μs
9.2.2a tPB_ON_SLOW EN/PB/VSENSE, Wait Time PB, ON request, slow PB, falling Edge 540 600 660 ms
9.2.2b tPB_ON_FAST EN/PB/VSENSE, Wait Time PB, ON request, fast PB, falling Edge 180 200 220 ms
9.2.3 tPB_OFF EN/PB/VSENSE, Wait Time PB, OFF request PB, falling Edge 7.2 8.0 8.8 s
9.2.4 tPB_RISE_DEGL EN/PB/VSENSE, Deglitch time PB, rising edge PB, rising Edge, applicable after the successful long-press-OFF-request 115 200 275 ms
9.2.5 tPB_INT_DEGL EN/PB/VSENSE, Deglitch time PB, rising or falling edge PB, rising or falling Edge 59 100 137 ms
9.2.6 tDEGL_EN_Rise_Slow EN/PB/VSENSE, DeglitchTime EN slow, rising EN, rising Edge 45 50 55 ms
9.2.7 tDEGL_EN_Rise_Fast EN/PB/VSENSE, DeglitchTime EN fast, rising EN, rising Edge 60 120 150 μs
9.2.8 tDEGL_EN_Fall EN/PB/VSENSE, DeglitchTime EN, falling EN, falling Edge 50 70 93 μs
9.2.9 tDEGL_VSENSE_Rise VSENSE rising: only gated by VSYSPOR_Rising and VSENSE-voltage VSENSE, rising Edge N/A
9.2.10 tDEGL_VSENSE_Fall EN/PB/VSENSE, DeglitchTime VSENSE, falling, regardless of fast/slow setting VSENSE, falling Edge 50 70 93 μs
9.2.11 tDEGL_EN/VSENSE_I2C EN/VSENSE falling edge deglitch time after I2C-triggered shutdown EN/VSENSE falling edge after previous shutdown request by I2C (shorter than 9.2.8) 12.5 25 37.5 μs
9.2.12 tDEGL_RESET MODE/RESET, Deglitch Time RESET RESET, rising and falling Edge 90 120 150 μs
9.2.13 tDEGL_MFP Deglitch Time MODE/STBY, MODE(not/RESET), VSEL_SD/VSEL_DDR Rising and falling Edge 90 120 150 μs
9.2.14 tDEGL_GPIO Deglitch Time GPIO Rising and falling Edge 6.6 15.6 18 μs
9.2.15 tREACTION_ON ON-request propagation delay (after deglitch) Includes oscillator startup, sampling delay and reaction delay (excluding deglitch)  75 103 µs
9.2.16 tREACTION_OFF OFF-request propagation delay (after deglitch) Includes sampling delay and reaction delay (excluding deglitch)  39 56 73.5 µs