JAJSOZ4A June 2023 – June 2024 TPS6521905
PRODUCTION DATA
STBY state is a low-power mode of operation intended to support system standby. The mode can be entered by the MODE/STBY pin, if configured as 'STBY' or by an I2C-command to STBY_I2C_CTRL in MFP_CTRL register. Typically, the majority of power rails are turned off with the exception of rails required by the SoC during this state. Which rails power down in STBY state can be configured in STBY_1_CONFIG and STBY_2_CONFIG register.
The monitoring functions are all available: Under-voltage- (UV), Short-to-GND- (SCG) and Over-current- (OC) detection, thermal warning (WARM) and thermal-shutdown (TSD/HOT) remain active.
The device enters ACTIVE state if STBY is de-asserted or an I2C command is received (provided VIO-supply remained active). Before starting the STBY to ACTIVE sequence, disabled rails are discharged. In case this fails to complete within 80 ms, the device also runs into a timeout-condition and transitions to INITIALIZE state. The device sets bit TIMEOUT in the INT_TIMEOUT_RV_SD register and the fault flags for the rail that caused the shut-down.
The sequence into and out of STBY state is the same as for power-down respectively for power-up. Rails that remain on in STBY are skipped, but their respective slots are still executed.
Non-NVM-bits are not accessible for ~80 us after starting a transition into INITIALIZE state.